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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
This commit is contained in:
Eddie Hung
commit
32eef26ee2
67 changed files with 3620 additions and 590 deletions
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@ -221,3 +221,73 @@ check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
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\$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr
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design -load postopt
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select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
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\$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr
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design -load postopt
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select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
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\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr
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design -load postopt
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select -assert-count 1 t:$shift r:A_WIDTH=3 %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
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\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr
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design -load postopt
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select -assert-count 1 t:$shift r:A_WIDTH=10 %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
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\$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
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endmodule
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EOT
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check
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equiv_opt opt_expr -keepdc
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design -load postopt
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select -assert-count 1 t:$shift r:A_WIDTH=13 %i
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@ -1,6 +1,7 @@
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module test(input clk, input [3:0] bar, output [3:0] foo);
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module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
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reg [3:0] foo = 0;
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reg [3:0] last_bar = 0;
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reg [3:0] asdf = 4'b1xxx;
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always @*
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foo[1:0] <= bar[1:0];
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@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
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always @(posedge clk)
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last_bar <= bar;
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always @(posedge clk)
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asdf[3] <= bar[3];
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always @*
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asdf[2:0] = 3'b111;
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assert property (foo == {last_bar[3:2], bar[1:0]});
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endmodule
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@ -1,4 +1,3 @@
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module demo_001(y1, y2, y3, y4);
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output [7:0] y1, y2, y3, y4;
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@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3);
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assign y3 = 1 ? -1 : 'd0;
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endmodule
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module demo_003(output A, B);
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parameter real p = 0;
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assign A = (p==1.0);
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assign B = (p!="1.000000");
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endmodule
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module demo_004(output A, B, C, D);
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demo_003 #(1.0) demo_real (A, B);
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demo_003 #(1) demo_int (C, D);
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endmodule
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1
tests/techmap/.gitignore
vendored
1
tests/techmap/.gitignore
vendored
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@ -1 +1,2 @@
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*.log
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/*.mk
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96
tests/techmap/clkbufmap.ys
Normal file
96
tests/techmap/clkbufmap.ys
Normal file
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@ -0,0 +1,96 @@
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read_verilog <<EOT
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module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
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module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
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module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
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module latch (input e, d, output q); endmodule
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module clkgen (output o); endmodule
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module top(input clk1, clk2, clk3, d, e, output [4:0] q);
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wire clk4, clk5, clk6;
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dff s0 (.clk(clk1), .d(d), .q(q[0]));
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dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
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latch s2 (.e(clk3), .d(d), .q(q[2]));
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sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3]));
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dff s4 (.clk(clk4), .d(d), .q(q[4]));
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dff s5 (.clk(clk5), .d(d), .q(q[4]));
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dff s6 (.clk(clk6), .d(d), .q(q[4]));
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endmodule
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module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
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wire tmp;
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clkgen s7(.o(sclk4));
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clkgen s8(.o(sclk5));
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clkgen s9(.o(tmp));
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clkbuf s10(.i(tmp), .o(sclk6));
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dff s11(.clk(sclk4), .d(sd), .q(sq));
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endmodule
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EOT
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hierarchy -auto-top
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design -save ref
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# ----------------------
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design -load ref
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clkbufmap -buf clkbuf o:i
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select -assert-count 3 top/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk1 # Check there is one such fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
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select -set clk2 w:clk2 %a %co t:clkbuf %i
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select -assert-count 1 @clk2
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select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
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select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
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select -set clk5 w:clk5 %a %ci t:clkbuf %i
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select -assert-count 1 @clk5
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select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
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select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
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select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
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select -assert-count 1 @sclk4
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select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
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select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
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# ----------------------
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design -load ref
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setattr -set clkbuf_inhibit 0 w:clk1
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setattr -set clkbuf_inhibit 1 w:clk2
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clkbufmap -buf clkbuf o:i
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select -assert-count 2 top/t:clkbuf
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select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk1 # Check there is one such fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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# ----------------------
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design -load ref
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setattr -set clkbuf_inhibit 1 w:clk1
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setattr -set buffer_type "bufg" w:clk2
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 3 top/t:clkbuf
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select -assert-count 2 sub/t:clkbuf
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select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk1 # Check there is one such fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
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select -set clk2 w:clk2 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
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select -assert-count 1 @clk2 # Check there is one such fanout
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select -assert-count 1 @clk2 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
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select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0'
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# ----------------------
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design -load ref
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setattr -set buffer_type "none" w:clk1
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setattr -set buffer_type "bufr" w:clk2
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setattr -set buffer_type "bufr" w:sclk4
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setattr -set buffer_type "bufr" w:sclk5
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clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
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select -assert-count 0 w:clk1 %a %co t:clkbuf %i
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select -assert-count 0 w:clk2 %a %co t:clkbuf %i
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select -assert-count 0 top/t:clkbuf
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select -assert-count 1 sub/t:clkbuf
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8
tests/techmap/recursive.v
Normal file
8
tests/techmap/recursive.v
Normal file
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@ -0,0 +1,8 @@
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module top;
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sub s0();
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foo f0();
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endmodule
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module foo;
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sub s0();
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endmodule
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4
tests/techmap/recursive_map.v
Normal file
4
tests/techmap/recursive_map.v
Normal file
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@ -0,0 +1,4 @@
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module sub;
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sub _TECHMAP_REPLACE_ ();
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bar f0();
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endmodule
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3
tests/techmap/recursive_runtest.sh
Normal file
3
tests/techmap/recursive_runtest.sh
Normal file
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@ -0,0 +1,3 @@
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set -ev
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../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v
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@ -1,10 +1,20 @@
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#!/bin/bash
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#!/usr/bin/env bash
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set -e
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for x in *_runtest.sh; do
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echo "Running $x.."
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if ! bash $x &> ${x%.sh}.log; then
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tail ${x%.sh}.log
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echo ERROR
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exit 1
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{
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echo "all::"
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for x in *.ys; do
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echo "all:: run-$x"
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echo "run-$x:"
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echo " @echo 'Running $x..'"
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echo " @../../yosys -ql ${x%.ys}.log $x"
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done
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for s in *.sh; do
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if [ "$s" != "run-test.sh" ]; then
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echo "all:: run-$s"
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echo "run-$s:"
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echo " @echo 'Running $s..'"
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echo " @bash $s > ${s%.sh}.log 2>&1"
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fi
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done
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} > run-test.mk
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exec ${MAKE:-make} -f run-test.mk
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14
tests/various/mem2reg.ys
Normal file
14
tests/various/mem2reg.ys
Normal file
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@ -0,0 +1,14 @@
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read_verilog <<EOT
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module top;
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parameter DATADEPTH=2;
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parameter DATAWIDTH=1;
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(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
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(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
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endmodule
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EOT
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proc
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cd top
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select -assert-count 1 m:data1 a:src=<<EOT:4 %i
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select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
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select -assert-none a:mem2reg
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21
tests/various/pmgen_reduce.ys
Normal file
21
tests/various/pmgen_reduce.ys
Normal file
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@ -0,0 +1,21 @@
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test_pmgen -generate reduce
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hierarchy -top pmtest_test_pmgen_pm_reduce
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flatten; opt_clean
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design -save gold
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test_pmgen -reduce_chain
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design -stash gate
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design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
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design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
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miter -equiv -flatten -make_assert gold gate miter
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sat -verify -prove-asserts miter
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design -load gold
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test_pmgen -reduce_tree
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design -stash gate
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design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
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design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
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miter -equiv -flatten -make_assert gold gate miter
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sat -verify -prove-asserts miter
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