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6440 commits 122 branches 59 tags 73 MiB
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Author SHA1 Message Date
David Shah
e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah
f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
David Shah
fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
David Shah
c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
David Shah
7a563d0b92 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 13:23:42 +01:00
Eddie Hung
c39b1a6fcf Add comment about supporting $dffe in ice40_dsp 2019-08-01 15:13:18 -07:00
Eddie Hung
ed7540a46f Pack P register properly 2019-08-01 15:10:43 -07:00
Eddie Hung
105aaeaf59 Trim Y_WIDTH 2019-08-01 14:33:16 -07:00
Eddie Hung
65de9aaaa9 Add DSP_SIGNEDONLY back 2019-08-01 14:29:00 -07:00
Eddie Hung
915f4e34bf DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH 2019-08-01 13:20:34 -07:00
Eddie Hung
fc0b5d5ab6 Change $__softmul back to $mul 2019-08-01 12:45:14 -07:00
Eddie Hung
e19d33b003 Cope with sign extension in mul2dsp 2019-08-01 12:44:56 -07:00
Eddie Hung
332b86491d Revert "Do not do sign extension in techmap; let packer do it" 
This reverts commit 595a8f032f.
 2019-08-01 12:17:14 -07:00
Eddie Hung
ed303b07b7 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-01 12:02:16 -07:00
Eddie Hung
7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Eddie Hung
c54a39069d CO is sign extension only if signed multiplier 2019-08-01 10:00:49 -07:00
Eddie Hung
e3c39cc450 Fix typo 2019-08-01 10:00:01 -07:00
Eddie Hung
e8a2d10982
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map 
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
 2019-08-01 09:38:55 -07:00
Eddie Hung
d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung
60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung
e4a638c292 Restore old CO behaviour 2019-07-31 15:45:15 -07:00
Eddie Hung
84c7a562e5 Helper: SigSpec::operator[] to accept negative indices 2019-07-31 12:18:03 -07:00
Clifford Wolf
acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer 
Call "read_verilog" with -defer from "read"
 2019-07-31 13:30:52 +02:00
Eddie Hung
66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Eddie Hung
b4f38cca77
Merge pull request #1228 from YosysHQ/dave/yy_buf_size 
verilog_lexer: Increase YY_BUF_SIZE to 65536
 2019-07-29 09:16:09 -07:00
David Shah
ccf759864a
Merge pull request #1234 from mmicko/fix_gzip_no_exist 
Fix case when file does not exist
 2019-07-29 15:50:20 +01:00
Miodrag Milanovic
3e4307c104 Fix case when file does not exist 2019-07-29 12:29:13 +02:00
Clifford Wolf
5be5bd0fb6 Update README to use "read" instead of "read_verilog" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:40:30 +02:00
Clifford Wolf
fc462c8243 Call "read_verilog" with -defer from "read" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-29 10:29:36 +02:00
David Shah
6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip 
Add support for gzip'd input files
 2019-07-27 07:40:38 +01:00
Eddie Hung
2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Eddie Hung
07e38d8d5c Update test_autotb doc to reflect default value of zero 2019-07-26 12:37:30 -07:00
Eddie Hung
8cecad5059 Add doc for "test_autotb -seed" option 2019-07-26 12:26:54 -07:00
Eddie Hung
4c25d1a76f Pop the CO bit from O 2019-07-26 10:27:30 -07:00
Eddie Hung
c1a05f4557 Allow adders/accumulators with 33 bits using CO output 2019-07-26 10:15:36 -07:00
David Shah
482926cbd3 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 15:53:21 +01:00
David Shah
92694ea3a9 verilog_lexer: Increase YY_BUF_SIZE to 65536 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 13:35:39 +01:00
David Shah
da6701c4cd Fix frontend auto-detection for gzipped input 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:29:05 +01:00
David Shah
933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Eddie Hung
a02d1720a7 Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-25 10:49:26 -07:00
Eddie Hung
c5e31ac9c3 Bump abc to fix &mfs bug 2019-07-25 10:48:58 -07:00
Clifford Wolf
eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Clifford Wolf
2bdd8003d3
Merge pull request #1219 from jakobwenzel/objIterator 
made ObjectIterator comply with Iterator Interface
 2019-07-25 17:19:11 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
Jakob Wenzel
70882a8070 replaced std::iterator with using statements 2019-07-25 09:51:09 +02:00
David Shah
ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Eddie Hung
d6a289d3e3
Merge pull request #1222 from koriakin/s6-example 
Add a simple example for Spartan 6
 2019-07-24 10:51:03 -07:00