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Code Activity
8412 commits 99 branches 53 tags 46 MiB
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2744 commits

Author SHA1 Message Date
Eddie Hung
7b2bccb3d3 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09 Print ".en=" only if there is an enable signal 2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef Escape IdStrings 2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf More sane naming of submod 2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0 Add -set_attr option, -unpart to take attr name 2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb Do not use log_signal() for empty SigSpec to prevent "{ }" 2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186 Call submod once, more meaningful submod names, ignore largest domain 2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 22:28:35 -08:00
Eddie Hung
cba3073026 submod to bitty rather bussy, for bussy wires used as input and output 2019-11-22 20:53:58 -08:00
Eddie Hung
900c806d4e Move clkpart into passes/hierarchy 2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81 Constant driven signals are also an input to submodules 2019-11-22 17:23:51 -08:00
Eddie Hung
89a4a4d90f Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a Oops 2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4 Only action if there is more than one clock domain 2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4 Replace TODO 2019-11-22 16:58:08 -08:00
Eddie Hung
0806b8e398 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 16:50:56 -08:00
Eddie Hung
6a52897aee sigmap(wire) should inherit port_output status of POs 2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb Brackets 2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5 Entry in Makefile.inc 2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d New 'clkpart' to {,un}partition design according to clock/enable 2019-11-22 15:35:51 -08:00
Clifford Wolf
03fb92ed6f Add "opt_mem" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 17:45:22 +01:00
Eddie Hung
c4ec42ac38 When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ 
Since they should be captured downwards from the owning flop
 2019-11-21 16:17:03 -08:00
David Shah
ca99b1ee8d proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 20:46:41 +00:00
Eddie Hung
729c6b93e8 endomain -> ctrldomain 2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
David Shah
7ff5d6d30a memory_collect: Copy attr from RTLIL::Memory to cell 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 13:58:03 +00:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst 
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
 2019-11-17 10:42:30 +01:00
David Shah
f5804a84fd wreduce: Don't trim zeros or sext when not matching ARST_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname 
Add "autoname" pass and use it in "synth_ice40"
 2019-11-14 18:03:44 +01:00
Clifford Wolf
07c854b7af Add "autoname" pass and use it in "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes 
flowmap: fix a few crashes
 2019-11-13 11:57:17 +00:00
Clifford Wolf
4be5a0fd7c Update fsm_detect bugfix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32 Bugfix in fsm_detect 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-12 14:26:02 +01:00
whitequark
c68722818a flowmap: when doing mincut, ensure source is always in X, not X̅. 
Fixes #1475.
 2019-11-12 00:15:43 +00:00
whitequark
eef32195bd flowmap: don't break if that creates a k+2 (and larger) LUT either. 
Fixes #1405.
 2019-11-11 23:13:00 +00:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849 Fix dffmux peepopt init handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5 Move GENERATE_PATTERN macro to separate utility header 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441 Disable left-over log_debug in peepopt_dffmux.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 10:43:47 +02:00
Eddie Hung
304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung
ea54b5ea61 Revert "Be mindful that sigmap(wire) could have dupes when checking \init" 
This reverts commit f46ac1df9f.
 2019-10-08 12:41:24 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00