Mohamed Gaber
d986ee91ac
CMake: integrate silimate additions and extensions
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- update CMakeLists.txt to load two new files:
- SilimateConfig.cmake: sets Silimate configuration options and defaults
- SilimateVerific.cmake: compiles Verific library, optionally with Silimate modifications
- include silimate tests in test Makefile
2026-06-10 20:27:52 +03:00
Mohamed Gaber
e58125b605
Merge remote-tracking branch 'upstream/main' into silimate
2026-06-09 16:22:51 +03:00
Miodrag Milanović
693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize
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verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
2026-06-04 05:43:04 +00:00
Miodrag Milanovic
ce280354cf
Update CI scripts for CMake
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Co-authored-by: Catherine <whitequark@whitequark.org>
2026-06-03 08:58:11 +00:00
Catherine
a727e7f6e7
Migrate build system to CMake
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See #5895 for details.
This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
Emil J. Tywoniak
80bdbaa010
genrtlil: don't avoid emitting flops for nosync
2026-05-29 11:37:08 +02:00
Krystine Sherwin
5f53410db7
verific: Fix negative array dimensions
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Recurse over memory dimensions once, doing both our min/max address checking and parsing out the initval. This also avoids problems with negative numbers (if `a < b` and one or both are negative, `a` might be the intended `max_addr_chunk`).
Fix sub addressing, where we use some but not all of the current dimension's bits.
2026-05-29 18:40:25 +12:00
Krystine Sherwin
21966ef496
verific: Fix non-contiguous memory init
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Recurse over nested type ranges to calculate true addresses.
2026-05-29 18:40:25 +12:00
Krystine Sherwin
099c664dc9
verific: Fix upto ranges
2026-05-29 18:40:23 +12:00
Krystine Sherwin
7cf0c55466
verific: Fix non-contiguous memory flattening
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May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic.
Still needs to adjust ascii init val addresses, but should work fine for read/write accesses.
2026-05-29 18:40:23 +12:00
Miodrag Milanovic
75dcbe03c6
Convert RTLIL::unescape_id of IdString to unescape()
2026-05-16 19:49:45 +02:00
Miodrag Milanovic
8bbc3c359c
Remove id2cstr uses in our code base
2026-05-16 19:49:45 +02:00
Miodrag Milanovic
4a7878b17f
Fixing couple more conversion errors
2026-05-14 15:58:58 +02:00
Miodrag Milanovic
9580ebabc5
log_id here was needed for unescaping
2026-05-14 12:35:01 +02:00
Codexplorer
e41b969da2
Refactored uses of log_id()
2026-05-08 20:59:24 -07:00
Akash Levy
e1aade6a1f
Update frontends/verific/verific.cc
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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-04-30 14:15:44 -07:00
Akash Levy
89a8250ae8
Update frontends/verific/verific.cc
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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-04-30 14:15:25 -07:00
Akash Levy
4d110a96bf
Localize external package/global net
2026-04-30 10:51:03 -07:00
Stan Lee
489fb6ea54
compilation err
2026-04-28 16:22:12 -07:00
Stan Lee
18dc5cc2cc
remove pointer
2026-04-28 16:21:23 -07:00
Stan Lee
48329bd36a
change to string for consistency
2026-04-28 16:20:00 -07:00
Stan Lee
6f5b52807c
whitespace
2026-04-28 16:18:36 -07:00
Stan Lee
dd6e440937
rename and clean
2026-04-28 16:16:57 -07:00
Stan Lee
e801ea4fdb
delete module frontend
2026-04-28 15:12:50 -07:00
Christopher D. Leary
390f09b89a
Support positional assignment patterns for unpacked arrays
2026-04-23 14:29:38 -07:00
Akash Levy
bf40364bd0
No operator optimization, but it passes all tests
2026-04-22 03:12:26 -07:00
Petter Reinholdtsen
a89e8fd869
Fixed spelling error in message of frontends/ast/genrtlil.cc.
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Patch by Ruben Undheim via the Debian project. The patch originated
as 0009-Some-spelling-errors-fixed.patch and was dated 2018-07-12
there.
See also issue #5805 .
2026-04-22 04:30:18 +02:00
Lofty
ed5d122174
Merge pull request #5793 from YosysHQ/lofty/abc-refactor-4
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read/write_xaiger2: further cleanup [sc-269]
2026-04-21 12:13:42 +00:00
Akash Levy
89d56882ba
Pullup/pulldown primitives
2026-04-15 12:37:18 -07:00
Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef
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Undefine set&reset behavior of $dffsr
2026-04-08 14:22:34 +00:00
Lofty
6d715784cd
read_xaiger2: further cleanup
2026-04-08 11:08:59 +01:00
Abhinav Tondapu
0f641f70b2
adding comments
2026-04-02 15:30:45 -07:00
Abhinav Tondapu
1f96d3209b
[ENG-1842] adding file dump from verific
2026-04-02 09:54:26 -07:00
Abhinav Tondapu
d5122ed2fa
[ENG-1827] ignore placeholder/empty ports from verific
2026-03-27 15:20:12 -07:00
Emil J. Tywoniak
ad7a776d73
genrtlil: even faster removeSignalFromCaseTree
2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
23ce4b8560
genrtlil: faster removeSignalFromCaseTree
2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
85013f9ed3
fixup! read_liberty: model clear_preset_variable correctly
2026-03-06 14:24:18 +01:00
Robert O'Callahan
13d9fffdb9
Work around std::reverse miscompilation with empty range
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This causes problems when compiling with fuzzing instrumenation enabled.
2026-03-06 02:03:21 +00:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment
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ast: Add support for array-to-array assignment
2026-03-05 11:10:12 +00:00
Andrew Pullin
6ac8c8cb05
ast: Add support for array-to-array assignment
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This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
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celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
126492742b
read_liberty: fix for msvc
2026-03-03 17:34:58 +01:00
Emil J. Tywoniak
22916aaab1
read_liberty: model clear_preset_variable correctly
2026-03-03 10:35:03 +01:00
Emil J. Tywoniak
857bc02710
liberty: warn if dffsr has clear&preset well defined
2026-03-03 10:34:29 +01:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
Akash Levy
bf4ce9d6f7
Import uniquify fix
2026-02-19 00:24:32 -08:00
Akash Levy
b7098e8383
Merge branch 'YosysHQ:main' into main
2026-02-18 09:44:25 -08:00
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check
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blifparse: add bounds check
2026-02-18 12:18:05 +01:00
