2119 commits

Author	SHA1	Message	Date
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00
Clifford Wolf	2c9bd23801	Added spice testbench to techlibs/cmos	2013-09-14 13:29:11 +02:00
Clifford Wolf	bbe5aa446b	Added spice backend	2013-09-14 11:23:45 +02:00
Clifford Wolf	6685ad436e	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	2013-08-27 13:12:26 +02:00
Clifford Wolf	5059b31660	Added simple xilinx7 technology mapping files	2013-08-22 20:31:04 +02:00
Clifford Wolf	a860efa8ac	Implemented same div-by-zero behavior as found in other synthesis tools	2013-08-15 21:00:06 +02:00
Clifford Wolf	c8763301b4	Added $div and $mod technology mapping	2013-08-09 17:09:24 +02:00
Clifford Wolf	ad9bbcbf40	Added $lut cells and abc lut mapping support	2013-07-23 16:19:34 +02:00
Clifford Wolf	7daeee340a	Fixed shift ops with large right hand side	2013-07-09 18:59:59 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	7f3f25841e	More sign-extension related fixes	2013-06-10 21:04:04 +02:00
Clifford Wolf	29d6ebd961	Implemented technology mapping for multipliers (using array multiplier)	2013-06-03 12:48:44 +02:00
Clifford Wolf	32dbf7752d	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	2013-04-07 16:42:29 +02:00
Clifford Wolf	d60fbaf664	Added EXTRA_TARGETS Makefile variable	2013-03-28 16:53:40 +01:00
Clifford Wolf	26f2439551	Tiny bugfix in simlib.v	2013-03-26 19:06:28 +01:00
Clifford Wolf	6960df7285	Fixed stdcells.v for $adff with undef reset value	2013-03-24 10:43:05 +01:00
Clifford Wolf	11789db206	More support code for $sr cells	2013-03-14 11:15:00 +01:00
Clifford Wolf	6543917fb8	added .gitignore files	2013-01-05 11:19:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00