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More support code for $sr cells

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Clifford Wolf 2013-03-14 11:15:00 +01:00
parent de823ce964
commit 11789db206
2 changed files with 50 additions and 1 deletions
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21
techlibs/simlib.v
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@ -642,6 +642,27 @@ endmodule
// --------------------------------------------------------
module \$sr (S, R, Q);
parameter WIDTH = 0;
input CLK;
input [WIDTH-1:0] S, R;
output reg [WIDTH-1:0] Q;
integer i;
always @(S, R)
for (i = 0; i < WIDTH; i = i+1) begin
if (R[i])
Q[i] <= 0;
else if (S[i])
Q[i] <= 1;
end
endmodule
// --------------------------------------------------------
module \$dff (CLK, D, Q);
parameter WIDTH = 0;