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Tiny bugfix in simlib.v

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Clifford Wolf 2013-03-26 19:06:28 +01:00
parent 7a99349de4
commit 26f2439551
1 changed files with 0 additions and 1 deletions
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techlibs/simlib.v
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@ -646,7 +646,6 @@ module \$sr (S, R, Q);
parameter WIDTH = 0;
input CLK;
input [WIDTH-1:0] S, R;
output reg [WIDTH-1:0] Q;