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Switch back to main Verific without VHDL support

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This commit is contained in:
Akash Levy 2026-02-18 21:57:14 -08:00
parent 9a30512cff
commit 3e9a5c68b1
5 changed files with 4 additions and 7 deletions
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2
Makefile
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@ -17,7 +17,7 @@ ENABLE_GHDL := 0
ENABLE_SLANG := 0
ENABLE_VERIFIC := 1
ENABLE_VERIFIC_SYSTEMVERILOG := 1
ENABLE_VERIFIC_VHDL := 1
ENABLE_VERIFIC_VHDL := 0
ENABLE_VERIFIC_HIER_TREE := 1
ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0

2
tests/verific/README.md
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@ -2,6 +2,8 @@
## Disabled
- `import_warning_operator`: no VHDL
- `mixed_flist`: no VHDL
- `memory_semantics`: relies on initial values being retained, which we do not want
- `rom_case`: we need different behavior for multi-port memories
- `blackbox*`: we need different behavior for parametrized blackboxes

5
tests/verific/import_warning_operator.ys
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@ -1,5 +0,0 @@
logger -expect warning "import_warning_operator.vhd:[0-9]+.[0-9]+-[0-9]+.[0-9]+: Unsupported Verific operator: nor_4 \(fallback to gate level implementation provided by verific\)" 1
verific -vhdl import_warning_operator.vhd
verific -import top
logger -check-expected
design -reset

0
tests/verific/mixed_flist.ys → tests/verific/mixed_flist.ys.DISABLED
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2
verific

@ -1 +1 @@
Subproject commit 01ad443c3fff2a92c9473b69291ac32ef788683a
Subproject commit 4feaf1f923157af0ed064eab8e302647bd5fa1b7