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10265 commits 122 branches 59 tags 72 MiB
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1437 commits

Author SHA1 Message Date
Vamsi K Vytla
5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
 2020-04-27 09:44:24 -07:00
Eddie Hung
dd5f206d9e verific: recover wiretype/enum attr as part of import_attributes() 2020-04-27 08:43:54 -07:00
Eddie Hung
b52eccef3a Revert "verific: import enum attributes from verific" 
This reverts commit 5028e17f7d.
 2020-04-24 11:57:55 -07:00
Eddie Hung
d3555c667c verific: do not assert if wire not found; warn instead 2020-04-23 16:28:11 -07:00
Eddie Hung
5028e17f7d verific: import enum attributes from verific 2020-04-22 17:26:56 -07:00
Claire Wolf
9f1fb11b1d Clear current_scope when done with RTLIL generation, fixes #1837 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-22 14:51:20 +02:00
Marcelina Kościelnicka
06a344efcb ilang, ast: Store parameter order and default value information. 
Fixes #1819, #1820.
 2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
whitequark
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name 
ast, rpc: record original name of $paramod\* as \hdlname attribute
 2020-04-21 01:43:20 +00:00
Claire Wolf
35990b95ec Extend support for format strings in Verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-18 14:08:51 +02:00
whitequark
41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute. 
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
 2020-04-18 03:47:28 +00:00
Alberto Gonzalez
00d74f0b9c
Set Verilog source location for explicit blocks (begin ... end). 2020-04-17 06:23:03 +00:00
Alberto Gonzalez
10a814f978
Add Verilog source location information to AST_POSEDGE and AST_NEGEDGE nodes. 2020-04-17 06:16:59 +00:00
Alberto Gonzalez
9253497358
Add location information to AST_CONSTANT nodes. 2020-04-16 19:11:47 +00:00
Claire Wolf
e86ba3b94d Make mask-and-shift the default for bitselwrite 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-16 12:11:52 +02:00
Claire Wolf
e1fb12a4b9 Add LookaheadRewriter for proper bitselwrite support 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-16 12:11:07 +02:00
David Shah
4d02505820 ast: Fix handling of identifiers in the global scope 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 10:30:07 +01:00
Claire Wolf
4711fea6c0 Improved rewrite code for writing to bit slice (disabled for now) 
This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-15 17:44:37 +02:00
whitequark
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum 
ast/simplify: improve enum handling
 2020-04-15 14:16:50 +00:00
whitequark
2106f78bb1 ast/simplify: improve enum handling. 
Before this commit, enum values were serialized as attributes of form
  \enum_<width>_<value>
where <value> was a decimal signed integer.

This has multiple drawbacks:
  * Enums with large values would be hard to process for downstream
    tooling that cannot parse arbitrary precision decimals. (In fact
    Yosys also did not correctly process enums with large values,
    and would overflow `int`.)
  * Enum value attributes were not confined to their own namespace,
    making it harder for downstream tooling to enumerate all such
    attributes, as opposed to looking up any specific value.
  * Enum values could not include x or z, which are explicitly
    permitted in the SystemVerilog standard.

After this commit, enum values are serialized as attributes of form
  \enum_value_<value>
where <value> is a bit sequence of the appropriate width.
 2020-04-15 14:14:50 +00:00
Claire Wolf
9b4dab397e Fix 5bba9c3, closes #1876 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-14 21:05:07 +02:00
whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl 
support using previously declared types/localparams/parameters in package
 2020-04-14 12:40:00 +00:00
whitequark
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum 
duplicated enum item names should result in an error
 2020-04-14 12:39:28 +00:00
whitequark
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser 
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
 2020-04-13 08:40:45 +00:00
Alberto Gonzalez
8a84674a42
Clean up pseudo-private member usage in frontends/ilang/ilang_parser.y. 2020-04-13 04:22:00 +00:00
David Shah
0a178de1b3 verilog: Fix write to deleted object 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-12 18:49:09 +01:00
whitequark
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow 
Improve handling of integer literals in RTLIL frontend
 2020-04-09 04:02:57 +00:00
Henner Zeller
c15040c218 aigerparse: only define __STDC_FORMAT_MACROS it not already before. 2020-04-07 12:50:31 -07:00
Jeff Wang
dbfd6b7530 duplicated enum item names should result in an error 2020-04-07 02:30:11 -04:00
Jeff Wang
249876b614 support using previously declared types/localparams/params in package 
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
 2020-04-07 00:38:15 -04:00
whitequark
b494d4c656
read_ilang: improve style. NFC. 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-04-06 18:31:15 +00:00
whitequark
d22888ce74 read_ilang: improve error message for overly long wires. 
Fixes #1838.
 2020-04-06 10:33:02 +00:00
whitequark
ca70a1049f read_ilang: detect overflow of integer literals. 2020-04-06 10:32:02 +00:00
Eddie Hung
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice 
ast: cap dynamic range select to size of signal, suppresses warnings
 2020-04-02 12:27:10 -07:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings 
IdString: use more ID::*, make them easier to use, speed up IdString::in()
 2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe 
Adding error message for when size (width) of number literal is zero
 2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
David Shah
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc 
verilog: Add location info for generate constructs
 2020-04-01 20:55:24 +01:00
David Shah
c3997c77a5 verilog: Add location info for generate constructs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-01 18:47:20 +01:00
Eddie Hung
c22fb76664 ast: cap dynamic range select to size of signal, suppresses warnings 2020-04-01 09:59:23 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice 
ast: simplify to fully populate dynamic slicing case transformation
 2020-04-01 08:38:14 +02:00
Eddie Hung
5132f4099b ast: simplify to fully populate dynamic slicing case transformation 2020-03-31 11:52:14 -07:00
Diego H
c859bcf71b Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3 Adding error message for when size (width) of number literal is zero 2020-03-30 17:18:13 -06:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to fixup_ports(). 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines 
Add support for SystemVerilog-style `define to Verilog frontend
 2020-03-30 13:51:12 +02:00