mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 09:34:09 +00:00
Code Activity

Set Verilog source location for explicit blocks (begin ... end).

Browse source
This commit is contained in:
Alberto Gonzalez 2020-04-17 06:23:03 +00:00
parent 10a814f978
commit 00d74f0b9c
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 1 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
frontends/verilog/verilog_parser.y
View file

@ -2246,6 +2246,7 @@ behavioral_stmt:
exitTypeScope();
if ($4 != NULL && $8 != NULL && *$4 != *$8)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
delete $4;
delete $8;
ast_stack.pop_back();