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https://github.com/YosysHQ/yosys
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kernel: use more ID::*
This commit is contained in:
Eddie Hung
parent
164dd0f6b2
commit
fdafb74eb7
69 changed files with 843 additions and 841 deletions
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@ -117,7 +117,7 @@ struct ConstEvalAig
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sig2deps[output].insert(output);
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RTLIL::Cell *cell = sig2driver.at(output);
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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RTLIL::SigBit sig_a = cell->getPort(ID::A);
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sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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@ -126,7 +126,7 @@ struct ConstEvalAig
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compute_deps(sig_a, inputs);
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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@ -142,11 +142,11 @@ struct ConstEvalAig
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bool eval(RTLIL::Cell *cell)
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{
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RTLIL::SigBit sig_y = cell->getPort("\\Y");
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RTLIL::SigBit sig_y = cell->getPort(ID::Y);
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if (values_map.count(sig_y))
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return true;
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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RTLIL::SigBit sig_a = cell->getPort(ID::A);
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if (!eval(sig_a))
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return false;
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@ -162,7 +162,7 @@ struct ConstEvalAig
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}
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{
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RTLIL::SigBit sig_b = cell->getPort("\\B");
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RTLIL::SigBit sig_b = cell->getPort(ID::B);
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if (!eval(sig_b))
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return false;
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if (sig_b == State::S0) {
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@ -930,7 +930,7 @@ void AigerReader::post_process()
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for (auto cell : module->cells().to_vector()) {
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if (cell->type != "$lut") continue;
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auto y_port = cell->getPort("\\Y").as_bit();
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auto y_port = cell->getPort(ID::Y).as_bit();
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if (y_port.wire->width == 1)
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module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
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else
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@ -952,7 +952,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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current_module = new AstModule;
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current_module->ast = NULL;
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current_module->name = ast->str;
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current_module->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
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current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
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ast->location.first_column, ast->location.last_line, ast->location.last_column);
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current_module->set_bool_attribute("\\cells_not_processed");
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@ -1124,7 +1124,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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}
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if (ast->type == AST_INTERFACE)
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current_module->set_bool_attribute("\\is_interface");
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current_module->set_bool_attribute(ID::is_interface);
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current_module->ast = ast_before_simplify;
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current_module->nolatches = flag_nolatches;
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current_module->nomeminit = flag_nomeminit;
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@ -1389,8 +1389,8 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
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// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
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// new module.
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if (this->get_bool_attribute("\\initial_top")) {
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this->attributes.erase("\\initial_top");
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if (this->get_bool_attribute(ID::initial_top)) {
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this->attributes.erase(ID::initial_top);
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is_top = true;
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}
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@ -1400,7 +1400,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
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design->add(newmod);
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RTLIL::Module* mod = design->module(original_name);
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if (is_top)
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mod->set_bool_attribute("\\top");
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mod->set_bool_attribute(ID::top);
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// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
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mod->set_bool_attribute("\\interfaces_replaced_in_module");
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@ -1473,7 +1473,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
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// We copy the cell of the interface to the sub-module such that it
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// can further be found if it is propagated down to sub-sub-modules etc.
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RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name);
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new_subcell->set_bool_attribute("\\is_interface");
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new_subcell->set_bool_attribute(ID::is_interface);
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}
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else {
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log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
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@ -47,10 +47,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (gen_attributes)
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for (auto &attr : that->attributes) {
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@ -61,10 +61,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
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cell->setPort("\\A", arg);
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cell->setPort(ID::A, arg);
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cell->parameters["\\Y_WIDTH"] = result_width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -80,10 +80,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (that != NULL)
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for (auto &attr : that->attributes) {
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@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
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cell->setPort("\\A", sig);
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cell->setPort(ID::A, sig);
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cell->parameters["\\Y_WIDTH"] = width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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sig = wire;
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}
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@ -108,10 +108,10 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -125,11 +125,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
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cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
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cell->setPort("\\A", left);
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cell->setPort("\\B", right);
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cell->setPort(ID::A, left);
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cell->setPort(ID::B, right);
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cell->parameters["\\Y_WIDTH"] = result_width;
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cell->setPort("\\Y", wire);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -142,10 +142,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -155,10 +155,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
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cell->setPort("\\A", right);
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cell->setPort("\\B", left);
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cell->setPort("\\S", cond);
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cell->setPort("\\Y", wire);
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cell->setPort(ID::A, right);
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cell->setPort(ID::B, left);
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cell->setPort(ID::S, cond);
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cell->setPort(ID::Y, wire);
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return wire;
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}
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@ -199,7 +199,7 @@ struct AST_INTERNAL::ProcessGenerator
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{
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// generate process and simple root case
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proc = new RTLIL::Process;
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proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -221,7 +221,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto child : always->children)
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{
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if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
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child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
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child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
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found_global_syncs = true;
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}
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if (child->type == AST_EDGE) {
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@ -245,7 +245,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto child : always->children)
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if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
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if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
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child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
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child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
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continue;
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found_clocked_sync = true;
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if (found_global_syncs || found_anyedge_syncs)
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@ -335,7 +335,7 @@ struct AST_INTERNAL::ProcessGenerator
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} while (current_module->wires_.count(wire_name) > 0);
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RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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chunk.wire = wire;
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chunk.offset = 0;
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@ -470,7 +470,7 @@ struct AST_INTERNAL::ProcessGenerator
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case AST_CASE:
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{
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RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
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sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
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sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
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sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
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current_case->switches.push_back(sw);
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@ -504,7 +504,7 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
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current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
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last_generated_case = current_case;
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addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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for (auto node : child->children) {
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@ -525,7 +525,7 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.restore();
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}
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if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
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if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
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#if 0
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// this is a valid transformation, but as optimization it is premature.
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// better: add a default case that assigns 'x' to everything, and let later
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@ -873,12 +873,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// This is used by the hierarchy pass to know when it can replace interface connection with the individual
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// signals.
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RTLIL::Wire *wire = current_module->addWire(str, 1);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->start_offset = 0;
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wire->port_id = port_id;
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wire->port_input = true;
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wire->port_output = true;
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wire->set_bool_attribute("\\is_interface");
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wire->set_bool_attribute(ID::is_interface);
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if (children.size() > 0) {
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for(size_t i=0; i<children.size();i++) {
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if(children[i]->type == AST_INTERFACEPORTTYPE) {
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@ -910,7 +910,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
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current_module->connect(wire, val);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
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for (auto &attr : attributes) {
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@ -932,7 +932,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
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RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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wire->start_offset = range_right;
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wire->port_id = port_id;
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wire->port_input = is_input;
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@ -945,8 +945,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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wire->attributes[attr.first] = attr.second->asAttrConst();
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}
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if (is_wand) wire->set_bool_attribute("\\wand");
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if (is_wor) wire->set_bool_attribute("\\wor");
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if (is_wand) wire->set_bool_attribute(ID::wand);
|
||||
if (is_wor) wire->set_bool_attribute(ID::wor);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -963,7 +963,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
|
||||
|
||||
RTLIL::Memory *memory = new RTLIL::Memory;
|
||||
memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
memory->name = str;
|
||||
memory->width = children[0]->range_left - children[0]->range_right + 1;
|
||||
if (children[1]->range_right < children[1]->range_left) {
|
||||
|
|
@ -1018,7 +1018,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
|
||||
RTLIL::Wire *wire = current_module->addWire(str);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->name = str;
|
||||
if (flag_autowire)
|
||||
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
|
|
@ -1033,7 +1033,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
|
||||
RTLIL::Wire *current_wire = current_module->wire(str);
|
||||
if (current_wire->get_bool_attribute("\\is_interface"))
|
||||
if (current_wire->get_bool_attribute(ID::is_interface))
|
||||
is_interface = true;
|
||||
// Ignore
|
||||
}
|
||||
|
|
@ -1058,7 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
dummy_wire = current_module->wires_[dummy_wire_name];
|
||||
else {
|
||||
dummy_wire = current_module->addWire(dummy_wire_name);
|
||||
dummy_wire->set_bool_attribute("\\is_interface");
|
||||
dummy_wire->set_bool_attribute(ID::is_interface);
|
||||
}
|
||||
RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
|
||||
return tmp;
|
||||
|
|
@ -1375,10 +1375,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
|
||||
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
is_signed = id2ast->is_signed;
|
||||
|
|
@ -1413,7 +1413,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
id2ast->meminfo(mem_width, mem_size, addr_bits);
|
||||
|
|
@ -1480,7 +1480,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
|
|
@ -1488,7 +1488,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
|
||||
cell->setPort("\\A", check);
|
||||
cell->setPort(ID::A, check);
|
||||
cell->setPort("\\EN", en);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1525,7 +1525,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(str, "");
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
|
||||
cell->set_bool_attribute("\\module_not_derived");
|
||||
|
||||
|
|
@ -1668,7 +1668,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
|
||||
Cell *cell = current_module->addCell(myid, str.substr(1));
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->parameters["\\WIDTH"] = width;
|
||||
|
||||
if (attributes.count("\\reg")) {
|
||||
|
|
@ -1679,8 +1679,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
Wire *wire = current_module->addWire(myid + "_wire", width);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->setPort("\\Y", wire);
|
||||
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->setPort(ID::Y, wire);
|
||||
|
||||
is_signed = sign_hint;
|
||||
return SigSpec(wire);
|
||||
|
|
|
|||
|
|
@ -3364,10 +3364,10 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
|
|||
}
|
||||
|
||||
// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
|
||||
if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
|
||||
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
|
||||
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
|
||||
|
||||
if (type == AST_MODULE && get_bool_attribute("\\mem2reg"))
|
||||
if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
|
||||
children_flags |= AstNode::MEM2REG_FL_ALL;
|
||||
|
||||
dict<AstNode*, uint32_t> *proc_flags_p = NULL;
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
|
||||
for (auto cell : module->cells())
|
||||
if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
|
||||
module->connect(cell->getPort("\\Y"), cell->getPort("\\A"));
|
||||
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
|
||||
remove_cells.push_back(cell);
|
||||
}
|
||||
|
||||
|
|
@ -488,8 +488,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
|
||||
sopcell->parameters["\\DEPTH"] = 0;
|
||||
sopcell->parameters["\\TABLE"] = RTLIL::Const();
|
||||
sopcell->setPort("\\A", input_sig);
|
||||
sopcell->setPort("\\Y", output_sig);
|
||||
sopcell->setPort(ID::A, input_sig);
|
||||
sopcell->setPort(ID::Y, output_sig);
|
||||
sopmode = -1;
|
||||
lastcell = sopcell;
|
||||
}
|
||||
|
|
@ -498,8 +498,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
|
||||
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
|
||||
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
|
||||
cell->setPort("\\A", input_sig);
|
||||
cell->setPort("\\Y", output_sig);
|
||||
cell->setPort(ID::A, input_sig);
|
||||
cell->setPort(ID::Y, output_sig);
|
||||
lutptr = &cell->parameters.at("\\LUT");
|
||||
lut_default_state = RTLIL::State::Sx;
|
||||
lastcell = cell;
|
||||
|
|
@ -545,10 +545,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
|
|||
if (sopmode == -1) {
|
||||
sopmode = (*output == '1');
|
||||
if (!sopmode) {
|
||||
SigSpec outnet = sopcell->getPort("\\Y");
|
||||
SigSpec outnet = sopcell->getPort(ID::Y);
|
||||
SigSpec tempnet = module->addWire(NEW_ID);
|
||||
module->addNotGate(NEW_ID, tempnet, outnet);
|
||||
sopcell->setPort("\\Y", tempnet);
|
||||
sopcell->setPort(ID::Y, tempnet);
|
||||
}
|
||||
} else
|
||||
log_assert(sopmode == (*output == '1'));
|
||||
|
|
|
|||
|
|
@ -56,36 +56,36 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
|
|||
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
|
||||
{
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
|
||||
cell->setPort("\\A", A);
|
||||
cell->setPort("\\Y", module->addWire(NEW_ID));
|
||||
return cell->getPort("\\Y");
|
||||
cell->setPort(ID::A, A);
|
||||
cell->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
return cell->getPort(ID::Y);
|
||||
}
|
||||
|
||||
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
|
||||
{
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
|
||||
cell->setPort("\\A", A);
|
||||
cell->setPort("\\B", B);
|
||||
cell->setPort("\\Y", module->addWire(NEW_ID));
|
||||
return cell->getPort("\\Y");
|
||||
cell->setPort(ID::A, A);
|
||||
cell->setPort(ID::B, B);
|
||||
cell->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
return cell->getPort(ID::Y);
|
||||
}
|
||||
|
||||
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
|
||||
{
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
|
||||
cell->setPort("\\A", A);
|
||||
cell->setPort("\\B", B);
|
||||
cell->setPort("\\Y", module->addWire(NEW_ID));
|
||||
return cell->getPort("\\Y");
|
||||
cell->setPort(ID::A, A);
|
||||
cell->setPort(ID::B, B);
|
||||
cell->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
return cell->getPort(ID::Y);
|
||||
}
|
||||
|
||||
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
|
||||
{
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
|
||||
cell->setPort("\\A", A);
|
||||
cell->setPort("\\B", B);
|
||||
cell->setPort("\\Y", module->addWire(NEW_ID));
|
||||
return cell->getPort("\\Y");
|
||||
cell->setPort(ID::A, A);
|
||||
cell->setPort(ID::B, B);
|
||||
cell->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
return cell->getPort(ID::Y);
|
||||
}
|
||||
|
||||
static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
|
||||
|
|
@ -241,18 +241,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
|
|||
rerun_invert_rollback = false;
|
||||
|
||||
for (auto &it : module->cells_) {
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
|
||||
clk_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clk_sig) {
|
||||
clk_sig = it.second->getPort(ID::A);
|
||||
clk_polarity = !clk_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
|
||||
clear_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
|
||||
clear_sig = it.second->getPort(ID::A);
|
||||
clear_polarity = !clear_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
|
||||
preset_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(ID::A);
|
||||
preset_polarity = !preset_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
|
|
@ -260,8 +260,8 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
|
|||
}
|
||||
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
|
||||
cell->setPort("\\A", iq_sig);
|
||||
cell->setPort("\\Y", iqn_sig);
|
||||
cell->setPort(ID::A, iq_sig);
|
||||
cell->setPort(ID::Y, iqn_sig);
|
||||
|
||||
cell = module->addCell(NEW_ID, "");
|
||||
cell->setPort("\\D", data_sig);
|
||||
|
|
@ -284,7 +284,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
|
|||
|
||||
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
|
||||
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
|
||||
cell->setPort("\\S", preset_sig);
|
||||
cell->setPort(ID::S, preset_sig);
|
||||
cell->setPort("\\R", clear_sig);
|
||||
}
|
||||
|
||||
|
|
@ -324,18 +324,18 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
|
|||
rerun_invert_rollback = false;
|
||||
|
||||
for (auto &it : module->cells_) {
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
|
||||
enable_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == enable_sig) {
|
||||
enable_sig = it.second->getPort(ID::A);
|
||||
enable_polarity = !enable_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
|
||||
clear_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
|
||||
clear_sig = it.second->getPort(ID::A);
|
||||
clear_polarity = !clear_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
|
||||
preset_sig = it.second->getPort("\\A");
|
||||
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(ID::A);
|
||||
preset_polarity = !preset_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
|
|
@ -343,8 +343,8 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
|
|||
}
|
||||
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
|
||||
cell->setPort("\\A", iq_sig);
|
||||
cell->setPort("\\Y", iqn_sig);
|
||||
cell->setPort(ID::A, iq_sig);
|
||||
cell->setPort(ID::Y, iqn_sig);
|
||||
|
||||
if (clear_sig.size() == 1)
|
||||
{
|
||||
|
|
@ -354,24 +354,24 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
|
|||
if (clear_polarity == true || clear_polarity != enable_polarity)
|
||||
{
|
||||
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
|
||||
inv->setPort("\\A", clear_sig);
|
||||
inv->setPort("\\Y", module->addWire(NEW_ID));
|
||||
inv->setPort(ID::A, clear_sig);
|
||||
inv->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
|
||||
if (clear_polarity == true)
|
||||
clear_negative = inv->getPort("\\Y");
|
||||
clear_negative = inv->getPort(ID::Y);
|
||||
if (clear_polarity != enable_polarity)
|
||||
clear_enable = inv->getPort("\\Y");
|
||||
clear_enable = inv->getPort(ID::Y);
|
||||
}
|
||||
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
|
||||
data_gate->setPort("\\A", data_sig);
|
||||
data_gate->setPort("\\B", clear_negative);
|
||||
data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
|
||||
data_gate->setPort(ID::A, data_sig);
|
||||
data_gate->setPort(ID::B, clear_negative);
|
||||
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
|
||||
enable_gate->setPort("\\A", enable_sig);
|
||||
enable_gate->setPort("\\B", clear_enable);
|
||||
enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
|
||||
enable_gate->setPort(ID::A, enable_sig);
|
||||
enable_gate->setPort(ID::B, clear_enable);
|
||||
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
}
|
||||
|
||||
if (preset_sig.size() == 1)
|
||||
|
|
@ -382,24 +382,24 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
|
|||
if (preset_polarity == false || preset_polarity != enable_polarity)
|
||||
{
|
||||
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
|
||||
inv->setPort("\\A", preset_sig);
|
||||
inv->setPort("\\Y", module->addWire(NEW_ID));
|
||||
inv->setPort(ID::A, preset_sig);
|
||||
inv->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
|
||||
if (preset_polarity == false)
|
||||
preset_positive = inv->getPort("\\Y");
|
||||
preset_positive = inv->getPort(ID::Y);
|
||||
if (preset_polarity != enable_polarity)
|
||||
preset_enable = inv->getPort("\\Y");
|
||||
preset_enable = inv->getPort(ID::Y);
|
||||
}
|
||||
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
|
||||
data_gate->setPort("\\A", data_sig);
|
||||
data_gate->setPort("\\B", preset_positive);
|
||||
data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
|
||||
data_gate->setPort(ID::A, data_sig);
|
||||
data_gate->setPort(ID::B, preset_positive);
|
||||
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
|
||||
enable_gate->setPort("\\A", enable_sig);
|
||||
enable_gate->setPort("\\B", preset_enable);
|
||||
enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
|
||||
enable_gate->setPort(ID::A, enable_sig);
|
||||
enable_gate->setPort(ID::B, preset_enable);
|
||||
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
}
|
||||
|
||||
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ struct RpcModule : RTLIL::Module {
|
|||
|
||||
module.second->name = mangled_name;
|
||||
module.second->design = design;
|
||||
module.second->attributes.erase("\\top");
|
||||
module.second->attributes.erase(ID::top);
|
||||
design->modules_[mangled_name] = module.second;
|
||||
derived_design->modules_.erase(module.first);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
|
|||
Att *attr;
|
||||
|
||||
if (obj->Linefile())
|
||||
attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
|
||||
attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
|
||||
|
||||
// FIXME: Parse numeric attributes
|
||||
FOREACH_ATTRIBUTE(obj, mi, attr) {
|
||||
|
|
|
|||
|
|
@ -436,9 +436,9 @@ module_arg_opt_assignment:
|
|||
wire->str = ast_stack.back()->children.back()->str;
|
||||
if (ast_stack.back()->children.back()->is_input) {
|
||||
AstNode *n = ast_stack.back()->children.back();
|
||||
if (n->attributes.count("\\defaultvalue"))
|
||||
delete n->attributes.at("\\defaultvalue");
|
||||
n->attributes["\\defaultvalue"] = $2;
|
||||
if (n->attributes.count(ID::defaultvalue))
|
||||
delete n->attributes.at(ID::defaultvalue);
|
||||
n->attributes[ID::defaultvalue] = $2;
|
||||
} else
|
||||
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
|
||||
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
|
||||
|
|
@ -1511,24 +1511,24 @@ wire_name_and_opt_assign:
|
|||
bool attr_anyseq = false;
|
||||
bool attr_allconst = false;
|
||||
bool attr_allseq = false;
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
|
||||
delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
|
||||
ast_stack.back()->children.back()->attributes.erase("\\anyconst");
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
|
||||
delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
|
||||
ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
|
||||
attr_anyconst = true;
|
||||
}
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
|
||||
delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
|
||||
ast_stack.back()->children.back()->attributes.erase("\\anyseq");
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
|
||||
delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
|
||||
ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
|
||||
attr_anyseq = true;
|
||||
}
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
|
||||
delete ast_stack.back()->children.back()->attributes.at("\\allconst");
|
||||
ast_stack.back()->children.back()->attributes.erase("\\allconst");
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
|
||||
delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
|
||||
ast_stack.back()->children.back()->attributes.erase(ID::allconst);
|
||||
attr_allconst = true;
|
||||
}
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
|
||||
delete ast_stack.back()->children.back()->attributes.at("\\allseq");
|
||||
ast_stack.back()->children.back()->attributes.erase("\\allseq");
|
||||
if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
|
||||
delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
|
||||
ast_stack.back()->children.back()->attributes.erase(ID::allseq);
|
||||
attr_allseq = true;
|
||||
}
|
||||
if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
|
||||
|
|
@ -1552,9 +1552,9 @@ wire_name_and_opt_assign:
|
|||
AstNode *wire = new AstNode(AST_IDENTIFIER);
|
||||
wire->str = ast_stack.back()->children.back()->str;
|
||||
if (astbuf1->is_input) {
|
||||
if (astbuf1->attributes.count("\\defaultvalue"))
|
||||
delete astbuf1->attributes.at("\\defaultvalue");
|
||||
astbuf1->attributes["\\defaultvalue"] = $3;
|
||||
if (astbuf1->attributes.count(ID::defaultvalue))
|
||||
delete astbuf1->attributes.at(ID::defaultvalue);
|
||||
astbuf1->attributes[ID::defaultvalue] = $3;
|
||||
}
|
||||
else if (astbuf1->is_reg || astbuf1->is_logic){
|
||||
AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
|
||||
|
|
@ -2355,12 +2355,12 @@ case_type:
|
|||
|
||||
opt_synopsys_attr:
|
||||
opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
|
||||
if (ast_stack.back()->attributes.count("\\full_case") == 0)
|
||||
ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
|
||||
if (ast_stack.back()->attributes.count(ID::full_case) == 0)
|
||||
ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
|
||||
} |
|
||||
opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
|
||||
if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
|
||||
ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
|
||||
if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
|
||||
ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
|
||||
} |
|
||||
/* empty */;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue