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Preserve 'signed'-ness of a verilog wire through RTLIL

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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
This commit is contained in:
Vamsi K Vytla 2020-04-27 09:44:24 -07:00
parent 3eb24809a1
commit 5f9cd2e2f6
6 changed files with 13 additions and 1 deletions
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1
frontends/ast/genrtlil.cc
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@ -1058,6 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
wire->is_signed = is_signed;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)

3
frontends/ilang/ilang_parser.y
View file

@ -192,6 +192,9 @@ wire_options:
wire_options TOK_UPTO {
current_wire->upto = true;
} |
wire_options TOK_SIGNED {
current_wire->is_signed = true;
} |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |