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Code Activity
5330 commits 122 branches 59 tags 73 MiB
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419 commits

Author SHA1 Message Date
Clifford Wolf
fecd3aa2b1 Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-09 18:47:08 +01:00
David Shah
4b49c0201e Merge pull request #1153 from YosysHQ/dave/fix_multi_mux 
memory_dff: Fix checking of feedback mux input when more than one mux
 2019-07-09 18:46:39 +01:00
Eddie Hung
fc87c010c5 autotest.sh to define _AUTOTB when test_autotb 2019-07-09 18:46:18 +01:00
Clifford Wolf
ef0823690c Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-07-09 18:44:57 +01:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog 
tests: Check that Icarus can parse arch sim models
 2019-06-27 12:31:15 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung
ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung
3910bc2ea6 Copy tests from eddie/fix1132 2019-06-27 06:01:50 -07:00
David Shah
71b046d639 tests: Check that Icarus can parse arch sim models 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 18:46:22 +01:00
Eddie Hung
ab6e8ce0f0 Add testcase from #335, fixed by #1130 2019-06-25 08:43:58 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710 
memory_dff: walk through more than one mux for computing read enable
 2019-06-25 17:34:44 +02:00
Eddie Hung
a701a2accf Add test 2019-06-24 18:32:58 -07:00
Eddie Hung
4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Eddie Hung
32f637ffdb Add more tests 2019-06-21 12:31:04 -07:00
Eddie Hung
ae8305ffcc Fix testcase 2019-06-21 12:13:00 -07:00
Eddie Hung
6ec8160981 Add more muxpack tests, with overlapping entries 2019-06-21 11:45:53 -07:00
Eddie Hung
63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118 
Make genvar a signed type
 2019-06-21 10:13:13 +02:00
Eddie Hung
844c42cef8 Missing a clean and opt_expr -mux_bool in test 2019-06-20 19:47:59 -07:00
Eddie Hung
75375a3fbc Add test 2019-06-20 19:47:59 -07:00
Eddie Hung
c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Eddie Hung
d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung
b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung
b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Clifford Wolf
a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf
6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Eddie Hung
45c2a5f876 Add shregmap -tech xilinx test 2019-06-12 08:34:06 -07:00
Eddie Hung
c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung
1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung
a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
Eddie Hung
58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung
b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung
1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung
e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung
65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung
abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00
Eddie Hung
0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Clifford Wolf
6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983 
elaboration system tasks
 2019-06-07 13:39:46 +02:00
Clifford Wolf
f01a61f093 Rename implicit_ports.sv test to implicit_ports.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 13:12:25 +02:00
Clifford Wolf
a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00