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Merge pull request #1147 from YosysHQ/clifford/fix1144

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Improve specify dummy parser
This commit is contained in:
Clifford Wolf 2019-07-03 12:30:37 +02:00 • committed by David Shah
parent d105e2f03f
commit fecd3aa2b1
3 changed files with 26 additions and 82 deletions
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11
tests/various/specify.v
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@ -7,9 +7,11 @@ module test (
if (EN) Q <= D;
specify
if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
`endif
endspecify
endmodule
@ -28,3 +30,10 @@ module test2 (
(B => Q) = 1.5;
endspecify
endmodule
module issue01144(input clk, d, output q);
specify
(posedge clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule

2
tests/various/specify.ys
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@ -54,3 +54,5 @@ equiv_struct
equiv_induct -seq 5
equiv_status -assert
design -reset
read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v