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7560 commits 93 branches 53 tags 45 MiB
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2484 commits

Author SHA1 Message Date
Eddie Hung
c6d15c9aad Revert "Update doc for equiv_opt" 
This reverts commit a274b7cc86.
 2019-10-03 10:07:03 -07:00
Eddie Hung
a274b7cc86 Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request from YosysHQ/eddie/equiv_opt_async2sync 
equiv_opt to call async2sync when not -multiclock like SymbiYosys
 2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 14:58:23 +02:00
Eddie Hung
8474c5b366
Merge pull request from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Miodrag Milanovic
3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Eddie Hung
a39505e329 equiv_opt to call async2sync when not -multiclock like SymbiYosys 2019-09-27 12:59:10 -07:00
Eddie Hung
aebbfffd71 Ooops AREG and BREG to default to -1 2019-09-27 11:57:53 -07:00
Marcin Kościelnicki
fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in .
 2019-09-27 18:34:12 +02:00
Eddie Hung
26657037b8 Update doc with max cascade chain of 20 2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d Do not always zero out C (e.g. during cascade breaks) 2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df Update doc 2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab Zero out ports 2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1 xilinx_dsp_cascade to also cascade AREG and BREG 2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0 Try recursive pmgen for P cascade 2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024 CREG to check for \keep 2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8 Remove newline 2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5 Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) 2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989 Reject if (* init *) present 2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818 Rework xilinx_dsp postAdd for new wreduce call 2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984 Fix memory issue since SigSpec& could be invalidated 2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483 unextend only used in init 2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Clifford Wolf
b432c9b44b Improve "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd Add "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-24 18:08:59 +02:00
Eddie Hung
44374b1b2b "abc_padding" attr for blackbox outputs that were padded, remove them later 2019-09-23 21:58:40 -07:00
Eddie Hung
e556d48d45 Set [AB]CASCREG to legal values 2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde Comment to explain separating CREG packing 2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125 Separate out CREG packing into new pattern, to avoid conflict with PREG 2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665 Move log_debug("\n") later 2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605 Move unextend initialisation later 2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5 Use new port() overload once more 2019-09-23 13:00:44 -07:00
Eddie Hung
bcee87a457 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-23 10:58:28 -07:00
N. Engelhardt
3bed4cb18a fix show command for macos 2019-09-23 17:47:05 +02:00
Eddie Hung
ec08a031b5 Revert abc9.cc 2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e Trim mismatched connection to be same (smallest) size 2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7 Fix first testcase in 2019-09-20 17:51:27 -07:00
Eddie Hung
53817b8575 Use new port/param overload in pmg 2019-09-20 14:21:22 -07:00
Eddie Hung
d122083a11 Output pattern matcher items as log_debug() 2019-09-20 12:42:28 -07:00
Eddie Hung
95644b00cb OPMODE is port not param 2019-09-20 12:37:29 -07:00
Eddie Hung
3fb839e255 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-20 12:21:36 -07:00
Eddie Hung
eb597431f0 Do not run xilinx_dsp_cascadeAB for now 2019-09-20 12:18:37 -07:00
Eddie Hung
0bca366bcd WIP for xiinx_dsp_cascadeAB 2019-09-20 12:07:14 -07:00
Eddie Hung
b0ad2592be Run until convergence 2019-09-20 12:04:16 -07:00
Eddie Hung
1b892ca1be Cleanup ice40_dsp.pmg 2019-09-20 12:03:45 -07:00
Eddie Hung
d88903e610 Cleanup xilinx_dsp 2019-09-20 12:03:25 -07:00
Eddie Hung
1809f463fb More exceptions 2019-09-20 12:03:10 -07:00
Eddie Hung
70c5444b25 Update doc 2019-09-20 10:07:54 -07:00
Eddie Hung
ed187ef1cf Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT 2019-09-20 10:00:09 -07:00