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8996 commits 101 branches 53 tags 48 MiB
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Author SHA1 Message Date
David Shah
c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
e0a6742935
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 
ecp5: Add support for mapping 36-bit wide PDP BRAMs
 2019-10-03 09:53:45 +01:00
Eddie Hung
e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung
278533fe59
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire 
RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
 2019-10-02 19:40:39 -07:00
Eddie Hung
e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung
d99810ad8a Refactor peepopt_dffmux and be sensitive to \init when trimming 2019-10-02 18:01:45 -07:00
Eddie Hung
e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung
62c66406ad log_dump() to support State enum 2019-10-02 17:49:07 -07:00
Eddie Hung
f46ac1df9f Be mindful that sigmap(wire) could have dupes when checking \init 2019-10-02 16:08:46 -07:00
Eddie Hung
c28d4b8047 Add test that is expecting to fail 2019-10-02 14:52:40 -07:00
Eddie Hung
265a655ef9 Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf 2019-10-02 12:43:35 -07:00
Eddie Hung
a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Clifford Wolf
6028f5df1a
Merge pull request #1428 from YosysHQ/clifford/fixbtor 
Fix btor back-end to use "state" instead of "input" for undef init bits
 2019-10-02 13:48:09 +02:00
Clifford Wolf
45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Clifford Wolf
a84a2d74c7 Fix btor back-end to use "state" instead of "input" for undef init bits 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 12:48:04 +02:00
Eddie Hung
5299884f04 More fixes 2019-10-01 13:41:08 -07:00
Eddie Hung
03ebe43e3e Escape Verilog identifiers for legality outside of Yosys 2019-10-01 13:05:56 -07:00
Miodrag Milanović
da347b9f7e
Merge pull request #1426 from YosysHQ/mmicko/fix_environ 
Define environ, fixes #1424
 2019-10-01 19:50:37 +02:00
Miodrag Milanovic
c026579c20 Define environ, fixes #1424 2019-10-01 18:45:07 +02:00
David Shah
b424d374db ecp5: Fix shuffle_enable port 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 14:14:46 +01:00
David Shah
7a1538cd36 ecp5: Add support for mapping 36-bit wide PDP BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 13:46:36 +01:00
Sergey
eb750670e3
run-test.sh Move $x at end of line. 2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix 2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic 2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line. 2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492 equiv_opt with -assert 2019-09-30 19:54:59 -07:00
Eddie Hung
f8d5e11aa7 Update resource count for alu.ys 2019-09-30 19:54:04 -07:00
Eddie Hung
369652d4b9 Add test 2019-09-30 17:20:39 -07:00
Eddie Hung
edc3780723 techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias 2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c Resolve FIXME on calling proc just once 2019-09-30 16:37:29 -07:00
Eddie Hung
f9bb335294 Cleanup $currQ from aigerparse 2019-09-30 16:36:42 -07:00
Eddie Hung
e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung
5e9ae90cbb Add explanation to abc_map.v 2019-09-30 15:39:24 -07:00
Eddie Hung
8b239ee707 Add quick test 2019-09-30 15:34:04 -07:00
Eddie Hung
f2f19df2d4 Add -select option to aigmap 2019-09-30 15:26:29 -07:00
Eddie Hung
eecfdda614 Cleanup 2019-09-30 15:24:03 -07:00
Eddie Hung
e0aa772663 Add comment 2019-09-30 15:19:02 -07:00
Eddie Hung
d963e8c2c6 Fix typo 2019-09-30 15:18:40 -07:00
Eddie Hung
d992858318 Move $x to end as per 7f0eec8 2019-09-30 15:15:14 -07:00
Eddie Hung
eeb86247c5 Update fsm.ys resource count 2019-09-30 15:14:41 -07:00
Eddie Hung
0bbd1b6364 Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352 2019-09-30 14:57:55 -07:00
Eddie Hung
0a1af434e8 Fix for svinterfaces 2019-09-30 14:52:04 -07:00
Eddie Hung
08b55a20e3 module->derive() to be lazy and not touch ast if already derived 2019-09-30 14:11:01 -07:00
Eddie Hung
74678227c7 Use a cell_cache to instantiate once rather than opt_merge call 2019-09-30 13:21:07 -07:00
Eddie Hung
a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung
bd8356799a Use derived module 2019-09-30 12:34:28 -07:00