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696 commits

Author SHA1 Message Date
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller
3101b9b8c9 Fix remaining log_file_error(); emit dependent file references in new line. 
There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
 2018-07-20 18:52:52 -07:00
Henner Zeller
68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Henner Zeller
1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Clifford Wolf
fe2ee833e1 Fix handling of signed memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 16:57:03 +02:00
Udi Finkelstein
73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Clifford Wolf
4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf
a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Udi Finkelstein
2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf
eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf
a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf
8364f509e3 Fix error handling for nested always/initial 2017-12-02 18:52:05 +01:00
Clifford Wolf
bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf
caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Udi Finkelstein
eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Clifford Wolf
dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Udi Finkelstein
7e391ba904 enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog 2017-09-26 09:19:56 +03:00
Udi Finkelstein
2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf
8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" 2017-06-07 12:30:24 +02:00
Clifford Wolf
5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf
1e927a51d5 Preserve string parameters 2017-02-23 15:39:13 +01:00
Clifford Wolf
4fb8007171 Fix incorrect "incompatible re-declaration of wire" error in tasks/functions 2017-02-14 15:10:59 +01:00
Clifford Wolf
3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf
78f65f89ff Fix bug in AstNode::mem2reg_as_needed_pass2() 2017-01-15 13:52:50 +01:00
Clifford Wolf
2d32c6c4f6 Fixed handling of local memories in functions 2017-01-05 13:19:03 +01:00
Clifford Wolf
81a9ee2360 Added handling of local memories and error for local decls in unnamed blocks 2017-01-04 16:03:04 +01:00
Clifford Wolf
dfb461fe52 Added Verilog $rtoi and $itor support 2017-01-03 17:40:58 +01:00
Clifford Wolf
70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf
2874914bcb Fixed anonymous genblock object names 2016-11-04 07:46:30 +01:00
Clifford Wolf
56e2bb88ae Some fixes in handling of signed arrays 2016-11-01 23:17:43 +01:00
Clifford Wolf
aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf
bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf
aaa99c35bd Added $past, $stable, $rose, $fell SVA functions 2016-09-19 01:30:07 +02:00
Clifford Wolf
ab18e9df7c Added assertpmux 2016-09-07 00:28:01 +02:00
Clifford Wolf
97583ab729 Avoid creation of bogus initial blocks for assert/assume in always @* 2016-09-06 17:34:42 +02:00
Clifford Wolf
aa25a4cec6 Added $anyconst support to yosys-smtbmc 2016-08-30 19:27:42 +02:00
Clifford Wolf
6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf
450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf
82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf
dbdd8927e7 Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() 2016-08-21 13:18:09 +02:00
Clifford Wolf
fe9315b7a1 Fixed finish_addr handling in $readmemh/$readmemb 2016-08-20 13:47:46 +02:00