This website requires JavaScript.
Explore
Help
Register
Sign In
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-04-07 01:54:10 +00:00
Code
Activity
dbdd8927e7
yosys
/
frontends
/
ast
History
Clifford Wolf
dbdd8927e7
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
2016-08-21 13:18:09 +02:00
..
ast.cc
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
2016-08-21 13:18:09 +02:00
ast.h
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00