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yosys/frontends/ast
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet!
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
..
ast.cc This PR should be the base for discussion, do not merge it yet! 2018-03-11 23:09:34 +02:00
ast.h This PR should be the base for discussion, do not merge it yet! 2018-03-11 23:09:34 +02:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc Add $allconst and $allseq cell types 2018-02-23 13:14:47 +01:00
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
simplify.cc This PR should be the base for discussion, do not merge it yet! 2018-03-11 23:09:34 +02:00