mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-27 02:45:52 +00:00
2b9c75f8e3
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) |
||
|---|---|---|
| .. | ||
| ast.cc | ||
| ast.h | ||
| dpicall.cc | ||
| genrtlil.cc | ||
| Makefile.inc | ||
| simplify.cc | ||