Iztok Jeras
bade16eb23
dfflibmap: changed error warning from 'wide' to 'word-level' to match documentation
2026-07-31 03:52:29 +02:00
Iztok Jeras
ef7df59724
dfflibmap: added warning about clear/preset priority mismatch
2026-07-31 03:50:50 +02:00
Iztok Jeras
10739e1da1
dfflibmap: extended tests with same testcases as dlatchmap
2026-07-31 03:50:50 +02:00
Iztok Jeras
4e8bb6428f
dlatchlibmap: added more formal testscases
2026-07-31 03:50:50 +02:00
Iztok Jeras
d8a26032f8
dfflibmap: picking first instead of last cell with smallest area
...
In a standard cell library cells are usually ordered from weakest to strongest.
Sometimes the two weakest cells have the same area.
Previously the stroner (last) of the two was selected,
now the weaker (first is selected).
2026-07-31 03:45:18 +02:00
Iztok Jeras
ce3c7f738f
dfflibmap: collected copies of the same code into a function
2026-07-31 03:45:18 +02:00
Iztok Jeras
7af81e3bfe
dfflibmap: updated dlatchlibmap tests so they pass
2026-07-31 03:45:18 +02:00
Iztok Jeras
e82c939cb4
dlatchlibmap: modified copies of dfflibmap* test files for dlatchlibmap tests
2026-07-31 03:45:15 +02:00
Iztok Jeras
3de774f578
dlatchlibmap: making a copy of test files dfflibmap* to dlatchlibmap*
2026-07-31 03:30:54 +02:00
Iztok Jeras
dca26937bf
dlatchlibmap: fixing failing test 'liberty/dff.lib' by updating the golden log output
2026-07-31 03:25:51 +02:00
Iztok Jeras
40f1df4c1f
frontends/liberty: support all \$_LATCH* type cells (copy/modify from FF code)
2026-07-31 03:25:51 +02:00
Iztok Jeras
24dc1c6dc6
dfflibmap: simpler handling of cells with inverted data input polarity
2026-07-31 00:37:05 +02:00
Iztok Jeras
705751e1cb
dfflibmap: recommend running opt_merge pass after dfflibmap
2026-07-31 00:37:05 +02:00
Iztok Jeras
19e1e7fc16
dfflibmap: support for mapping latch cells
2026-07-31 00:37:05 +02:00
Iztok Jeras
16ae5ebf5c
dfflibmap: fixing apparent typo in testcase
2026-07-31 00:37:05 +02:00
Iztok Jeras
18edee9df5
dfflegalize: make it explicit in the documentation, that the pass operates on FFs and LATCHes
2026-07-31 00:37:05 +02:00
Iztok Jeras
7f0328a8d1
documentation: avoid documentation rendering issue
2026-07-31 00:37:05 +02:00
Miodrag Milanović
9bc23d383f
Merge pull request #6070 from YosysHQ/update_abc
...
Update ABC as per 2026-07-30
2026-07-30 17:05:48 +00:00
Miodrag Milanović
5c15b0b5a1
Merge pull request #6071 from YosysHQ/mmicko/test_disable
...
nexus: disable dsp test, takes very long
2026-07-30 16:34:15 +00:00
Miodrag Milanovic
130e39b06d
nexus: disable dsp test, takes very long
2026-07-30 17:46:25 +02:00
Emil J
c03bbc3309
Merge pull request #6069 from YosysHQ/emil/liberty-flop-fix-polarity
...
read_liberty: fix set&reset polarity
2026-07-30 15:34:24 +00:00
Miodrag Milanovic
c3b5607d05
Update ABC as per 2026-07-30
2026-07-30 17:02:50 +02:00
Emil J. Tywoniak
5f5f8b99b1
liberty: cleanup
2026-07-30 16:44:12 +02:00
nella
4821ed17b4
Merge pull request #5929 from YosysHQ/nella/fuse-2
...
Add register absorption for MULT* for Nexus (fix #5917 ).
2026-07-29 00:29:16 +00:00
nella
c1377426c9
Merge branch 'main' into nella/fuse-2
2026-07-29 01:41:37 +02:00
Emil J. Tywoniak
ef69127001
liberty: refactor out constant bools
2026-07-28 16:39:08 +02:00
Emil J
07a615a283
Merge pull request #6068 from YosysHQ/emil/aigmap-remove-unused-cache
...
aigmap: remove unused and_cache
2026-07-27 20:40:51 +00:00
Emil J. Tywoniak
82914a0204
dfflibmap: error on wide registers in design
2026-07-27 22:24:28 +02:00
Emil J. Tywoniak
db2b3a22e9
liberty: remove optimization to simplify control flow, fixing polarities in set&reset behavior modeling
2026-07-27 22:09:57 +02:00
Emil J. Tywoniak
c50290fdab
dfflibmap: fix formal verilog test so that it actually maps all flops
2026-07-27 22:08:39 +02:00
Emil J. Tywoniak
1a1d9494da
dfflibmap: check formal verilog test actually maps all flops
2026-07-27 22:06:22 +02:00
Emil J. Tywoniak
6585661740
aigmap: remove unused and_cache
2026-07-27 16:50:38 +02:00
Miodrag Milanović
2c28591b8e
Merge pull request #6067 from donn/force_static_ffi
...
wheels: force static libffi in build
2026-07-27 13:11:49 +00:00
Mohamed Gaber
a216efad1c
wheels: force static libffi in build
...
- only build static libffi
- improve resilience of cibw environment variables
2026-07-27 15:40:23 +03:00
Emil J
5d2fbf8187
Merge pull request #5961 from YosysHQ/emil/opt_muxtree-fix-reconvergence
...
opt_muxtree: fix reconvergence
2026-07-27 09:08:13 +00:00
nella
511017acc1
Merge branch 'main' into nella/fuse-2
2026-07-24 12:20:35 +02:00
nella
526ab7aab3
Use Nexus DSP pipelined registers.
2026-07-24 12:10:07 +02:00
nella
5e59deecc3
Fix test desc.
2026-07-24 12:07:10 +02:00
nella
7defa51862
Merge pull request #6007 from YosysHQ/nella/fix-shift-fold
...
Fix wide shift count folded as truncated/signed negative count
2026-07-24 08:17:11 +00:00
Krystine Sherwin
29a6295d7c
tests/opt: Fix comments
2026-07-23 14:59:12 +12:00
Lofty
30fe16c7f1
Merge pull request #6061 from YosysHQ/lofty/remove-flowmap
...
flowmap: remove
2026-07-22 13:57:19 +00:00
Miodrag Milanović
bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only
...
Add dependencies to gtests
2026-07-22 13:39:05 +00:00
Miodrag Milanovic
5574994453
Add dependencies to gtests
2026-07-22 15:03:12 +02:00
Lofty
f0b5225134
flowmap: remove
2026-07-22 13:50:33 +01:00
Lofty
f9023e92b4
Merge pull request #6059 from drewbabel/fix-xilinx-srl-fdre-enable
...
xilinx_srl: keep the clock enable on FDRE shift registers
2026-07-22 10:33:29 +00:00
Lofty
b914a7802e
Merge pull request #5782 from YosysHQ/lofty/abc-refactor-1
...
abc: remove -fast (again)
2026-07-21 09:26:10 +00:00
Lofty
45e1de36b4
abc: remove -fast (again)
2026-07-21 09:50:14 +01:00
drewbabel
3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers
...
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.
Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
2026-07-20 23:59:40 -07:00
Miodrag Milanović
e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu
...
Add `symfpu` pass
2026-07-20 10:20:23 +00:00
Miodrag Milanovic
cfd80cb48e
Update constids to fix leaks
2026-07-20 11:53:55 +02:00
