mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-04 21:33:35 +00:00
Code Activity

dfflibmap: fix formal verilog test so that it actually maps all flops

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-07-27 22:08:39 +02:00
parent 1a1d9494da
commit c50290fdab
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/techmap/dfflibmap_proc_formal.ys
View file

@ -44,6 +44,7 @@ EOT
proc
opt
techmap
copy top top_unmapped
design -save start