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11006 commits 124 branches 59 tags 44 MiB
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Author SHA1 Message Date
Eddie Hung
9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung
c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Miodrag Milanovic
7fafaa896d do not require boost if pyosys is not used 2019-08-22 11:57:46 -07:00
Chris Shucksmith
68e673d687 require tcl-tk in Brewfile 2019-08-22 11:57:25 -07:00
Eddie Hung
2fe35f902b
Merge pull request #1322 from mmicko/pyosys_osx 
do not require boost if pyosys is not used
 2019-08-22 11:53:27 -07:00
Eddie Hung
6e8fda8bf0 Add doc 2019-08-22 11:52:24 -07:00
Miodrag Milanovic
e5dac8096d do not require boost if pyosys is not used 2019-08-22 20:43:52 +02:00
Eddie Hung
926cd10350
Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk 
require tcl-tk in Brewfile
 2019-08-22 11:32:44 -07:00
Eddie Hung
cabadb85e2 Add copyright 2019-08-22 11:25:19 -07:00
Eddie Hung
7a9031c48e Add CHANGELOG entry 2019-08-22 11:22:53 -07:00
Eddie Hung
36d94caec1 Remove shregmap -tech xilinx additions 2019-08-22 11:22:09 -07:00
Eddie Hung
9f3ed1726e pmgen to also iterate over all module ports 2019-08-22 11:15:16 -07:00
Eddie Hung
74bd190d3b Remove output_bits 2019-08-22 11:14:59 -07:00
Eddie Hung
231ddbf95c Forgot to set ud_variable.minlen 2019-08-22 11:02:17 -07:00
Eddie Hung
61639d5387 Do not run xilinx_srl_pm in fixed loop 2019-08-22 10:51:04 -07:00
Eddie Hung
7188972645 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:54 -07:00
Eddie Hung
d0b2973413 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-22 10:32:06 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Clifford Wolf
5e0f6c9ae5 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:54 +02:00
Clifford Wolf
e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Clifford Wolf
151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf
2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf
4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf
4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung
9245f0d3f5 Copy-paste typo 2019-08-22 08:43:44 -07:00
Chris Shucksmith
d0322e9584 require tcl-tk in Brewfile 2019-08-22 16:37:40 +01:00
Eddie Hung
6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung
9e31f01b34 Add cover() 2019-08-22 08:06:24 -07:00
Eddie Hung
d0ffe7544c Canonical form 2019-08-22 08:05:01 -07:00
Clifford Wolf
34a7c0209d
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg 
mem2reg to preserve user attributes and src
 2019-08-22 10:24:42 +02:00
Eddie Hung
bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung
d3a212ff91 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 21:53:55 -07:00
Eddie Hung
7d02d17b16 Reuse var 2019-08-21 19:18:40 -07:00
Eddie Hung
5c8344363f Revert "Trim shiftx_width when upper bits are 1'bx" 
This reverts commit 7e7965ca7b.
 2019-08-21 19:18:27 -07:00
Eddie Hung
c7859531c2 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 19:18:05 -07:00
Eddie Hung
7e7965ca7b Trim shiftx_width when upper bits are 1'bx 2019-08-21 18:43:17 -07:00
Eddie Hung
ed7be3e6b6 Add comment 2019-08-21 17:36:38 -07:00
Eddie Hung
15188033da Add variable length support to xilinx_srl 2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65 Rename pattern to fixed 2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf attribute -> attr 2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13 Use Cell::has_keep_attribute() 2019-08-21 15:41:46 -07:00
Eddie Hung
edec73fec1 abc9 to perform new 'map_ffs' before 'map_luts' 2019-08-21 15:37:55 -07:00
Eddie Hung
6fa9e03e4c xilinx_srl to support FDRE and FDRE_1 2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6 Fix polarity of EN_POL 2019-08-21 14:42:11 -07:00
whitequark
841903582f
Merge pull request #1315 from mmicko/fix_dependencies 
Fix test_pmgen deps
 2019-08-21 21:40:31 +00:00
Eddie Hung
a980f0d4be Add CLKPOL == 0 2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558 Reject if not minlen from inside pattern matcher 2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e Get wire via SigBit 2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658 Respect \keep on cells or wires 2019-08-21 13:42:03 -07:00