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Add CHANGELOG entry
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@ -27,6 +27,8 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added "opt_share" pass, run as part of "opt -full"
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- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
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- Removed "ice40_unlut"
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- Added "xilinx_srl" for Xilinx shift register extraction
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- Removed "shregmap -tech xilinx"
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Yosys 0.8 .. Yosys 0.8-dev
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--------------------------
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