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16702 commits 120 branches 64 tags 47 MiB
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Author SHA1 Message Date
Lofty
b71f5bb908 synth_analogdevices: update timing model and tests 2026-02-20 10:57:46 +00:00
Lofty
f07f4d53d1 analogdevices: double LUT RAM cost 2026-02-20 10:57:46 +00:00
Lofty
9d2070cb7b analogdevices: ignore $assert cells 2026-02-20 10:57:46 +00:00
Krystine Sherwin
bdef403d92 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-02-20 10:57:46 +00:00
Krystine Sherwin
935eaa72b9 analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-02-20 10:57:46 +00:00
Krystine Sherwin
e753f6c6ce analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-02-20 10:57:46 +00:00
Lofty
ccbb80dc36 analogdevices: LUT RAM only on positive edge 2026-02-20 10:57:46 +00:00
Lofty
9fdfaf3c79 analogdevices: DSP tweaks 2026-02-20 10:57:46 +00:00
Lofty
fa1c859d07 analogdevices: DSP inference 2026-02-20 10:57:46 +00:00
Lofty
9d5ddcb356 analogdevices: remove cells_xtra 2026-02-20 10:57:46 +00:00
Lofty
eee01fcf7d analogdevices: timings for t40lp 2026-02-20 10:57:46 +00:00
Lofty
13b4b8c6b9 analogdevices: use single tech param 2026-02-20 10:57:46 +00:00
Lofty
f234e553dd analogdevices: expreso does not care about clock buffers 2026-02-20 10:57:46 +00:00
Lofty
1f5e6d5c61 analogdevices: prepare for t40lp timings 2026-02-20 10:57:46 +00:00
Krystine Sherwin
4ba732d1dd analogdevices: Adding RBRAM2 and -tech 2026-02-20 10:57:45 +00:00
Krystine Sherwin
4ff97770f5 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-02-20 10:57:45 +00:00
Krystine Sherwin
e7eae91abf analogdevices: Update lutram.ys test 2026-02-20 10:57:45 +00:00
Krystine Sherwin
49e463bfcc analogdevices: Native LUTRAM primitives 2026-02-20 10:57:45 +00:00
Lofty
5cdda40f14 analogdevices: LUTRAM config 2026-02-20 10:57:45 +00:00
Lofty
3780857f59 analogdevices: update timing model 2026-02-20 10:57:45 +00:00
Lofty
e6849b081f I thought I removed this... 2026-02-20 10:57:45 +00:00
Lofty
d45282042e analogdevices: user retargeting 2026-02-20 10:57:45 +00:00
Lofty
0ee490041e analogdevices: more housekeeping 2026-02-20 10:57:45 +00:00
Lofty
1690678911 analogdevices: remove some extra cells! 2026-02-20 10:57:45 +00:00
Lofty
bdf767e65e test suite 2026-02-20 10:57:45 +00:00
Lofty
9055d99215 synth_analogdevices: remove scopeinfo cells 2026-02-20 10:57:45 +00:00
Lofty
80f7d0ee6f Create synth_analogdevices 2026-02-20 10:57:45 +00:00
Krystine Sherwin
094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks 
aigerparse: add some bounds checks
 2026-02-20 11:53:49 +01:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Emil J
53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion 
modtools: fix database sanity
 2026-02-20 10:49:28 +01:00
Miodrag Milanović
679156d323
Merge pull request #5686 from YosysHQ/version_bump 
Automatic version bump
 2026-02-19 09:52:22 +01:00
Emil J. Tywoniak
abc7563a35 modtools: add ModIndex unit test 2026-02-18 22:15:44 +01:00
Emil J. Tywoniak
c75d80905a modtools: fix database sanity on wire name swap 2026-02-18 21:23:21 +01:00
Gus Smith
29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Miodrag Milanovic
5bb31485b7 Display repo and branch when applicable 2026-02-18 13:34:36 +01:00
Emil J. Tywoniak
62f19cb3a9 modtools: fix port_del db erase 2026-02-18 12:20:36 +01:00
Emil J
33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
Miodrag Milanovic
63068f9b8f count relative to version tag, and ignore non existing 2026-02-16 16:44:33 +01:00
Miodrag Milanović
ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Miodrag Milanovic
0090aa96b6 Remove version bump action 2026-02-13 14:22:33 +01:00
Miodrag Milanovic
adf8b6b0d8 Add +post to version if from tarbal 2026-02-13 14:22:10 +01:00
Miodrag Milanovic
c7d88ded94 Make version bump automatic 2026-02-13 14:21:41 +01:00
Chris Hathhorn
1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
github-actions[bot]
e2f0c4d9a0 Bump version 2026-02-13 00:35:27 +00:00
Miodrag Milanovic
bb7aa7d208 Cleanup of yml files 2026-02-12 14:56:45 +01:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic
e5b3e9fc1f This one should run only vanilla-tests 2026-02-12 14:08:49 +01:00
Miodrag Milanovic
c6e48f4bea These are tests from other Makefile 2026-02-12 14:06:08 +01:00
Miodrag Milanovic
cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00