gatecat
38a24ec5cc
gatemate: Add LUT tree library script
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Co-authored-by: Claire Xenia Wolf <claire@clairexen.net>
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
gatecat
7c756c9959
gatemate: Add preliminary sim models for LUT tree structures
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
Marcelina Kościelnicka
71dfbf33b2
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
2022-06-02 23:16:12 +02:00
Patrick Urban
5d08688054
gatemate: Fix minor issues with memory_libmap ( #3343 )
2022-05-27 23:35:26 +02:00
Marcelina Kościelnicka
2a2dc12eb6
gatemate: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
2dcb0797f0
machxo2: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
9d11575856
efinix: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
f4d1426229
anlogic: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9
ice40: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c
xilinx: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
e4d811561c
gowin: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Rick Luiken
414dc25a96
Add missing parameters for ecp5
2022-04-25 15:31:41 +01:00
Tim Pambor
30bc0d26ea
gowin: Add oscillator primitives
2022-03-28 13:33:24 +02:00
Marcelina Kościelnicka
be9595e18f
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
YRabbit
19b7633aca
gowin: add support for Double Data Rate primitives
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-14 23:14:21 +01:00
Lofty
9f7a55c99f
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
YRabbit
22d9bbb308
gowin: Remove unnecessary attributes
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
YRabbit
9b3cd4f0d8
gowin: Add support for true differential output
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
Marcelina Kościelnicka
d0f4d0b153
ecp5: Do not use specify in generate in cells_sim.v.
2022-02-21 17:52:31 +01:00
Marcelina Kościelnicka
3a62fa0c97
gowin: Add remaining block RAM blackboxes.
2022-02-12 11:48:57 +01:00
Marcelina Kościelnicka
f61f2a4078
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
Marcelina Kościelnicka
ac2bb70b52
ecp5: Fix DPR16X4 sim model.
2022-02-09 09:02:13 +01:00
Marcelina Kościelnicka
958c3a46ad
nexus: Fix arith_map CO signal.
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Fixes #3187 .
2022-02-06 13:05:30 +01:00
Xing GUO
0520e99968
Fix the help message of synth_quicklogic.
2022-01-31 02:23:59 +08:00
Marcelina Kościelnicka
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
gatecat
f699c4ba58
nexus: Fix BB sim model
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-19 18:14:24 +00:00
Miodrag Milanovic
36482680d5
Removed dbits 8 since 9 will always be picked
2022-01-19 08:51:25 +01:00
Miodrag Milanović
4525e419f6
Merge pull request #3120 from Icenowy/anlogic-bram
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anlogic: support BRAM mapping
2022-01-19 08:49:58 +01:00
Lofty
d015c2b48a
intel_alm: disable 256x40 M10K mode
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This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
2021-12-22 00:42:33 +01:00
Icenowy Zheng
c2b7ad3b28
anlogic: support BRAM mapping
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Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.
Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
Lofty
a31c8a82be
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
Patrick Urban
cb41209095
synth_gatemate Revert cascade A/B port mixup
2021-11-13 21:53:25 +01:00
Patrick Urban
decdc743db
synth_gatemate: Remove iob_map invokation
2021-11-13 21:53:25 +01:00
Patrick Urban
0d871b6c49
synth_gatemate: Add block RAM cascade support
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* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
2021-11-13 21:53:25 +01:00
Patrick Urban
285ec0547b
synth_gatemate: Remove obsolete iob_map
2021-11-13 21:53:25 +01:00
Patrick Urban
81964d6d6f
synth_gatemate: Update pass
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* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
2021-11-13 21:53:25 +01:00
Patrick Urban
74aee88e81
synth_gatemate: Remove specify blocks
2021-11-13 21:53:25 +01:00
Patrick Urban
05f24adca9
synth_gatemate: Remove gatemate_bramopt pass
2021-11-13 21:53:25 +01:00
Patrick Urban
4bee908ae8
synth_gatemate: Revise block RAM read modes and initialization
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* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
Patrick Urban
3f4ccdf2f5
synth_gatemate: Remove unsupported FF initialization
2021-11-13 21:53:25 +01:00
Patrick Urban
d592bd93b8
synth_gatemate: Rename multiplier factor parameters
2021-11-13 21:53:25 +01:00
Patrick Urban
6825de6343
synth_gatemate: Registers are uninitialized
2021-11-13 21:53:25 +01:00
Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
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* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
Patrick Urban
cfcc38582a
synth_gatemate: Apply review remarks
2021-11-13 21:53:25 +01:00
Patrick Urban
240d289fff
synth_gatemate: Initial implementation
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Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-11-13 21:53:25 +01:00
Marcelina Kościelnicka
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
Pepijn de Vos
4bf8deacbb
synth_gowin: move splitnets to after iopadmap ( #2435 )
2021-11-07 18:00:18 +01:00
Pepijn de Vos
a3eec687e0
Remove noalu from synth_gowin json output as Apicula now supports it
2021-11-07 03:04:21 +01:00
