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ecp5: Fix DPR16X4 sim model.

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This commit is contained in:
Marcelina Kościelnicka 2022-02-09 05:35:05 +01:00
parent 23d062fea3
commit ac2bb70b52
1 changed files with 1 additions and 1 deletions

2
techlibs/ecp5/cells_sim.v
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@ -204,7 +204,7 @@ module TRELLIS_DPR16X4 (
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
mem[i] <= INITVAL[4*i +: 4];
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;