mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

iopadmap: Add native support for negative-polarity output enable.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-11-09 11:22:48 +01:00
parent 4871d8f199
commit 15b0d717ed
12 changed files with 35 additions and 43 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/gowin/cells_map.v
View file

@ -122,14 +122,6 @@ module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$__GW_IOBUF (input I, OE, output O, inout IO);
IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .OEN(~OE), .IO(IO));
endmodule
module \$__GW_TBUF (input I, OE, output O);
TBUF _TECHMAP_REPLACE_ (.I(I), .OEN(~OE), .O(O));
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;

2
techlibs/gowin/synth_gowin.cc
View file

@ -240,7 +240,7 @@ struct SynthGowinPass : public ScriptPass
run("abc -dff -D 1", "(only if -retime)");
if (!noiopads || help_mode)
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
"-toutpad $__GW_TBUF OE:I:O -tinoutpad $__GW_IOBUF OE:O:I:IO", "(unless -noiopads)");
"-toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO", "(unless -noiopads)");
}
if (check_label("map_ffs"))

4
techlibs/machxo2/cells_map.v
View file

@ -30,5 +30,5 @@ module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"
// IO- "$__" cells for the iopadmap pass.
module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
module \$__FACADE_TOUTPAD (input I, OE, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(~OE)); endmodule
module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(~OE)); endmodule
module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule
module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule

4
techlibs/machxo2/cells_sim.v
View file

@ -207,6 +207,6 @@ module \$__FACADE_OUTPAD (input I, output O); endmodule
(* blackbox *)
module \$__FACADE_INPAD (input I, output O); endmodule
(* blackbox *)
module \$__FACADE_TOUTPAD (input I, OE, output O); endmodule
module \$__FACADE_TOUTPAD (input I, T, output O); endmodule
(* blackbox *)
module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); endmodule
module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule

2
techlibs/machxo2/synth_machxo2.cc
View file

@ -185,7 +185,7 @@ struct SynthMachXO2Pass : public ScriptPass
{
if (!noiopad || help_mode)
{
run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top");
run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top");
run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]");
run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]");
}

8
techlibs/nexus/cells_map.v
View file

@ -53,14 +53,6 @@ module \$_DFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_ASYNCLSR #(1) _TECHM
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
module \$__NX_TINOUTPAD (input I, OE, output O, inout B);
BB _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .B(B));
endmodule
module \$__NX_TOUTPAD (input I, OE, output O);
OBZ _TECHMAP_REPLACE_ (.I(I), .T(~OE), .O(O));
endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;

2
techlibs/nexus/synth_nexus.cc
View file

@ -333,7 +333,7 @@ struct SynthNexusPass : public ScriptPass
else
run("techmap -map +/techmap.v -map +/nexus/arith_map.v");
if (help_mode || !noiopad)
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad $__NX_TOUTPAD OE:I:O -tinoutpad $__NX_TINOUTPAD OE:O:I:B A:top", "(skip if '-noiopad')");
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(skip if '-noiopad')");
run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");

8
techlibs/xilinx/cells_map.v
View file

@ -359,11 +359,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
else
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO);
IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO));
endmodule
module \$__XILINX_TOUTPAD (input I, OE, output O);
OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE));
endmodule

5
techlibs/xilinx/synth_xilinx.cc
View file

@ -558,9 +558,10 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_cells")) {
// Needs to be done before logic optimization, so that inverters (OE vs T) are handled.
// Needs to be done before logic optimization, so that inverters (inserted
// here because of negative-polarity output enable) are handled.
if (help_mode || !noiopad)
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(skip if '-noiopad')");
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top", "(skip if '-noiopad')");
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);