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Code Activity
13175 commits 122 branches 59 tags 72 MiB
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2250 commits

Author SHA1 Message Date
Eddie Hung
7e86c8bcfb Fix B_WIDTH > DSP_B_MAXWIDTH case 2019-08-01 10:01:43 -07:00
Miodrag Milanovic
28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Eddie Hung
d2c33863d0 Do not compute sign bit if result is zero 2019-07-31 16:04:19 -07:00
Eddie Hung
60c4887d15 For signed multipliers, compute sign bit separately... 2019-07-31 15:45:41 -07:00
Eddie Hung
66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Eddie Hung
2f71c2c219 Fix spacing 2019-07-26 15:30:51 -07:00
Clifford Wolf
eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
David Shah
ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Eddie Hung
c39ccc65e9 Add copyright header, comment on cascade 2019-07-24 10:49:09 -07:00
Dan Ravensloft
49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Eddie Hung
151c5c96c0 Typo for Y_WIDTH 2019-07-23 15:05:20 -07:00
Dan Ravensloft
67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
Eddie Hung
cb505c50d3 Remove debug 2019-07-22 16:14:15 -07:00
Eddie Hung
4d71ab384d Rename according to vendor doc TN1295 2019-07-22 15:08:26 -07:00
Eddie Hung
5e70b8a22b opt and wreduce necessary for -dsp 2019-07-22 13:48:33 -07:00
Eddie Hung
3a7aeb028d Use minimum sized width wires 2019-07-22 13:01:26 -07:00
Eddie Hung
47fd042b9f Indirection via $__soft_mul 2019-07-19 20:20:33 -07:00
Eddie Hung
595a8f032f Do not do sign extension in techmap; let packer do it 2019-07-19 15:50:13 -07:00
Eddie Hung
bba72f03dd Do not $mul -> $__mul if A and B are less than maxwidth 2019-07-19 11:54:26 -07:00
Eddie Hung
3dc3c749d5 Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold 2019-07-19 11:41:00 -07:00
Eddie Hung
1d14cec7fd Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too 2019-07-19 11:39:24 -07:00
Eddie Hung
7bdb3996e2 Merge branch 'xc7dsp' into ice40dsp 2019-07-19 10:28:38 -07:00
Eddie Hung
ca94c2d3c4 Fix typo in B 2019-07-19 10:27:44 -07:00
Eddie Hung
d439a830c6 Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp 2019-07-19 09:40:47 -07:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
Eddie Hung
2168568f43 Use sign_headroom instead 2019-07-19 09:16:13 -07:00
David Shah
3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung
bddd641290 Fix SB_MAC sim model -- do not sign extend internal products? 2019-07-18 21:03:54 -07:00
Eddie Hung
601fac97e4 Add params 2019-07-18 21:02:49 -07:00
Eddie Hung
a777be3091 Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 20:37:39 -07:00
Eddie Hung
0157043b97 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-18 20:36:48 -07:00
Eddie Hung
15c2a79ab9 Do not define `DSP_SIGNEDONLY macro if no exists 2019-07-18 16:04:58 -07:00
Eddie Hung
42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung
266c1ae122 synth_ice40 to decompose into 16x16 2019-07-18 15:38:09 -07:00
Eddie Hung
2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung
e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
Eddie Hung
8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung
5562cb08a4 Use single DSP_SIGNEDONLY macro 2019-07-18 13:09:55 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00
Eddie Hung
2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
Dan Ravensloft
50f5e29724 synth_intel: s/not family/no family/ 2019-07-18 17:28:21 +01:00
Eddie Hung
d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00