68 commits

Author	SHA1	Message	Date
Clifford Wolf	8a69759306	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	ff5c61b120	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
Clifford Wolf	a75f94ec4a	Run dffsr2dff in synth_xilinx	2016-02-13 08:20:19 +01:00
Clifford Wolf	17372d8abd	Added "abc -luts" option, Improved Xilinx logic mapping	2016-02-01 12:40:32 +01:00
Clifford Wolf	864808992b	Bugfix in Xilinx LUT mapping	2015-10-30 13:58:03 +01:00
Clifford Wolf	f42218682d	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Clifford Wolf	9596fe74de	Another bugfix for ice40 and xilinx brams_init make rules	2015-08-16 21:39:34 +02:00
Clifford Wolf	aedcfd6fd3	Fixed Makefile rules for generated share files	2015-08-16 21:15:07 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	c329233f0d	Added output args to synth_ice40	2015-05-26 17:08:53 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	3481f46d1e	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
Clifford Wolf	7319951145	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
Clifford Wolf	229825e1b8	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
Clifford Wolf	b00cad81d7	Towards DRAM support in Xilinx flow	2015-04-09 08:17:14 +02:00
Clifford Wolf	8520b7fbe0	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Clifford Wolf	d19866615b	Added Xilinx test case for initialized brams	2015-04-06 13:27:11 +02:00
Clifford Wolf	4389d9306e	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
Clifford Wolf	c52a4cdeed	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00
Clifford Wolf	4d34d031f9	Added "stat" to "synth" and "synth_xilinx"	2015-02-15 13:25:15 +01:00
Clifford Wolf	881dcd8af9	Added final checks to "synth" and "synth_xilinx"	2015-02-15 13:00:00 +01:00
Clifford Wolf	853e949c0e	Disabled (unused) Xilinx tristate buffers	2015-02-04 16:33:59 +01:00
Clifford Wolf	bebbf2e5a4	no support for 6-series xilinx devices	2015-02-01 23:06:44 +01:00
Clifford Wolf	3cbfa3815e	Removed old XST-based xilinx examples	2015-02-01 17:10:46 +01:00
Clifford Wolf	816fe6bbe0	Added Xilinx example for Basys3 board	2015-02-01 17:09:34 +01:00
Clifford Wolf	1b159bc955	Added missing ports and parameters to xilinx brams	2015-02-01 15:42:59 +01:00
Clifford Wolf	909a95182b	Fixed xilinx FDSE sim model	2015-01-24 11:03:22 +01:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
Clifford Wolf	8d295730e5	Refactoring of memory_bram and xilinx brams	2015-01-18 19:05:29 +01:00
Clifford Wolf	279a18c9a3	Added synth_xilinx -retime -flatten	2015-01-17 20:47:18 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	dff8bd3b2a	Added dff2dffe to synth_xilinx	2015-01-16 15:49:15 +01:00
Clifford Wolf	7bde74cd2a	Added more FF types to xilinx/cells.v	2015-01-16 15:24:54 +01:00
Clifford Wolf	6b09153320	Fixed xilinx bram clock inverted config	2015-01-16 15:11:56 +01:00
Clifford Wolf	fd8c8d4fd3	Added FF cells to xilinx/cells_sim.v	2015-01-16 14:59:40 +01:00
Clifford Wolf	b197279f3c	Added Xilinx MUXF7 and MUXF8 support	2015-01-15 13:50:04 +01:00
Clifford Wolf	153d3dd4e0	Various cleanups in synth_xilinx command	2015-01-13 13:20:32 +01:00
Clifford Wolf	1d96277f5d	Added add_share_file Makefile macro	2015-01-08 00:23:18 +01:00
Clifford Wolf	38dfc5c580	added minimalistic xilinx sim models	2015-01-08 00:05:11 +01:00
Clifford Wolf	d1e38693d5	More Xilinx bram cleanups	2015-01-07 01:59:36 +01:00
Clifford Wolf	584c5f3937	Cleanups in xilinx bram descriptions	2015-01-07 01:28:18 +01:00
Clifford Wolf	08c13f635c	Xilinx RAMB36/RAMB18 memory_bram support complete	2015-01-06 23:54:33 +01:00
Clifford Wolf	ec2eef89fa	Towards Xilinx bram support	2015-01-06 23:21:52 +01:00
Clifford Wolf	7cc5192125	small fix in xilinx/brams.v	2015-01-06 17:21:18 +01:00
Clifford Wolf	9474928672	Towards Xilinx bram support	2015-01-06 15:26:33 +01:00
Clifford Wolf	4a0b3a5423	Various small improvements to synth_xilinx	2015-01-06 14:37:50 +01:00