mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
yosys/techlibs/xilinx
History
Clifford Wolf d19866615b Added Xilinx test case for initialized brams
2015-04-06 13:27:11 +02:00
..
example_basys3 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
tests Added Xilinx test case for initialized brams 2015-04-06 13:27:11 +02:00
arith_map.v Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
brams.txt Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
brams_bb.v Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
brams_map.v Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00
cells_map.v Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
cells_sim.v Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Makefile.inc Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
synth_xilinx.cc Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00