Clifford Wolf 0bc95f1e04 Added "yosys -D" feature		2016-04-21 23:28:37 +02:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
arith_map.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
cells_map.v	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
cells_sim.v	Disabled (unused) Xilinx tristate buffers	2015-02-04 16:33:59 +01:00
cells_xtra.sh	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
cells_xtra.v	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
drams.txt	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
drams_bb.v	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
drams_map.v	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
Makefile.inc	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
synth_xilinx.cc	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00