mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
9331 commits 123 branches 59 tags 44 MiB
Commit graph

994 commits

Author SHA1 Message Date
Eddie Hung
eec314e262 Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
Eddie Hung
ac2aff9e28 Fix abc9 with (* keep *) wires 2019-04-23 16:11:39 -07:00
Eddie Hung
bfd71e0990 Fix abc9 with (* keep *) wires 2019-04-23 16:11:14 -07:00
Clifford Wolf
e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
846eb5ea98 Add $specify2/$specify3 support to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
0bf9d0087c Add support for $assert/$assume/$cover to write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Eddie Hung
8f30019b68 Revert "Temporarily remove 'r' extension" 
This reverts commit eaf3c24772.
 2019-04-22 17:41:21 -07:00
Eddie Hung
eaf3c24772 Temporarily remove 'r' extension 2019-04-22 11:54:19 -07:00
Eddie Hung
b780c0a7de Allow POs to be PIs in XAIG 2019-04-22 11:22:29 -07:00
Eddie Hung
4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf
0e0c80fac8 Add support for zero-width signals to Verilog back-end, fixes #948 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 19:44:42 +02:00
Eddie Hung
caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Clifford Wolf
f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox 
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
 2019-04-20 20:51:54 +02:00
Eddie Hung
76bba49182 Fixes for simple_abc9 tests 2019-04-19 15:47:36 -07:00
Clifford Wolf
148caecca3 Change "ne" to "neq" in btor2 output 
we need to do this because they changed the parser:
e97fc9ceda

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-19 21:17:12 +02:00
Eddie Hung
35f44f3ae8 Do not assume inst_module is always present 2019-04-19 08:44:53 -07:00
Eddie Hung
3544a7cd7b ignore_boxes -> holes_mode 2019-04-19 08:37:10 -07:00
Eddie Hung
8f93999129 Revert "write_json to not write contents (cells/wires) of whiteboxes" 
This reverts commit 4ef03e19a8.
 2019-04-18 23:05:59 -07:00
Eddie Hung
6bdf98d591 Add flop support for write_xaiger 2019-04-18 17:43:13 -07:00
Eddie Hung
b531efd6d9 Spelling 2019-04-18 17:35:16 -07:00
Eddie Hung
4c327cf316 Use new -wb flag for ABC flow 2019-04-18 10:32:41 -07:00
Eddie Hung
4ef03e19a8 write_json to not write contents (cells/wires) of whiteboxes 2019-04-18 10:32:00 -07:00
Eddie Hung
79881141e2 write_json to not write contents (cells/wires) of whiteboxes 2019-04-18 10:30:45 -07:00
Eddie Hung
8fe0a961b3 Merge remote-tracking branch 'origin/clifford/whitebox' into xaig 2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung
23cd2e5de0 Fix $anyseq warning and cleanup 2019-04-17 16:03:29 -07:00
Eddie Hung
1ec5f18346 Cope with inout ports 2019-04-17 14:43:45 -07:00
Eddie Hung
2b860809e9 Stop topological sort at abc_flop_q 2019-04-17 12:28:19 -07:00
Eddie Hung
d59185f1d6 Remove init* from xaiger, also topo-sort cells for box flow 2019-04-17 11:08:42 -07:00
Eddie Hung
5c134980c4 Optimise 2019-04-16 21:05:44 -07:00
Eddie Hung
e7a8955818 CIs before PIs; also sort each cell's connections before iterating 2019-04-16 16:37:47 -07:00
Eddie Hung
55a3638c71 Port from xc7mux branch 2019-04-16 15:01:45 -07:00
Eddie Hung
fe0b421212 Output __const0__ and __const1__ CIs 2019-04-12 18:16:25 -07:00
Eddie Hung
686e772f0b ci_bits and co_bits now a list, order is important for ABC 2019-04-12 16:17:48 -07:00
Eddie Hung
c748391730 WIP 2019-04-12 14:13:11 -07:00
Eddie Hung
2217d59e29 Add non-input bits driven by unrecognised cells as ci_bits 2019-04-10 18:06:33 -07:00
Eddie Hung
bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Jim Lawson
73b87e7807 Refine memory support to deal with general Verilog memory definitions. 2019-04-01 15:02:12 -07:00
Clifford Wolf
1eff8be8f0 Add support for memory initialization to write_btor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:40:01 +01:00
Clifford Wolf
e78f5a3055 Fix BTOR output tags syntax in writye_btor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:39:42 +01:00
Clifford Wolf
bacca57537 Fix smtbmc.py handling of zero appended steps 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf
04e920337b Fix a syntax bug in ilang backend related to process case statements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:50:20 +01:00
Clifford Wolf
53b28b3f01
Merge pull request #869 from cr1901/win-shell 
Install launcher executable when running yosys-smtbmc on Windows.
 2019-03-14 16:43:23 +01:00
William D. Jones
ff15cf9b1f Install launcher executable when running yosys-smtbmc on Windows. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2019-03-13 13:49:16 -04:00
Clifford Wolf
20c6a8c9b0 Improve determinism of IdString DB for similar scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 20:12:28 +01:00
Clifford Wolf
94f995ee37 Fix signed $shift/$shiftx handling in write_smt2 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:19:41 -08:00
Clifford Wolf
5dfc7becca Use SVA label in smt export if available 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:31:46 -08:00
Jim Lawson
d6c4dfb902 Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails 
Mark dff_init.v as expected to fail since it uses "initial value".
 2019-03-04 13:37:23 -08:00
Clifford Wolf
03237de686 Fix "write_edif -gndvccy" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 12:59:07 -08:00
Clifford Wolf
241901461a Add "write_verilog -siminit" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 15:03:03 -08:00