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https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
Remove init* from xaiger, also topo-sort cells for box flow
This commit is contained in:
Eddie Hung
parent
116176e151
commit
d59185f1d6
1 changed files with 155 additions and 93 deletions
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@ -20,6 +20,8 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -46,9 +48,8 @@ struct XAigerWriter
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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pool<SigBit> initstate_bits;
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//pool<SigBit> initstate_bits;
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vector<std::pair<SigBit,int>> ci_bits, co_bits;
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dict<IdString, unsigned> type_map;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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@ -58,11 +59,11 @@ struct XAigerWriter
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dict<SigBit, int> ordered_outputs;
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dict<SigBit, int> ordered_latches;
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dict<SigBit, int> init_inputs;
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int initstate_ff = 0;
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vector<Cell*> box_list;
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//dict<SigBit, int> init_inputs;
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//int initstate_ff = 0;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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@ -76,10 +77,10 @@ struct XAigerWriter
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{
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aig_map[bit] = -1;
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if (initstate_bits.count(bit)) {
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log_assert(initstate_ff > 0);
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aig_map[bit] = initstate_ff;
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} else
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//if (initstate_bits.count(bit)) {
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// log_assert(initstate_ff > 0);
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// aig_map[bit] = initstate_ff;
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//} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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@ -170,8 +171,35 @@ struct XAigerWriter
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if (!bit.wire->port_input)
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unused_bits.erase(bit);
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc_box_seen = false;
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for (auto cell : module->cells())
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{
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toposort.node(cell->name);
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for (const auto &conn : cell->connections())
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{
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// HACK!!!
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if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
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continue;
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if (yosys_celltypes.cell_known(cell->type)) {
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if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
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continue;
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if (cell->type == "$memrd" && conn.first == "\\DATA")
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continue;
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}
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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@ -204,58 +232,92 @@ struct XAigerWriter
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continue;
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}
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if (cell->type == "$initstate")
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{
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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undriven_bits.erase(Y);
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initstate_bits.insert(Y);
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continue;
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}
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//if (cell->type == "$initstate")
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//{
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// SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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// undriven_bits.erase(Y);
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// initstate_bits.insert(Y);
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// continue;
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//}
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RTLIL::Module* box_module = module->design->module(cell->type);
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bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
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cell->connections_.sort(RTLIL::sort_by_id_str());
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input) {
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/*if (!w->port_input)*/ {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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/*if (!output_bits.count(b))*/
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if (abc_box)
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co_bits.emplace_back(b, 0);
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else if (b.wire) {
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if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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Wire *w = b.wire;
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if (!w) continue;
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input) {
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if (!w->port_input) {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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output_bits.insert(b);
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if (!b.wire->port_input)
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unused_bits.erase(b);
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unused_bits.erase(b);
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}
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}
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}
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if (is_output) {
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SigBit O = sigmap(b);
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/*if (!input_bits.count(O))*/
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if (abc_box)
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ci_bits.emplace_back(O, 0);
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else {
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if (is_output) {
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SigBit O = sigmap(b);
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input_bits.insert(O);
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if (!O.wire->port_output)
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undriven_bits.erase(O);
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}
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}
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}
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if (!type_map.count(cell->type))
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type_map[cell->type] = type_map.size()+1;
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}
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else
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abc_box_seen = true;
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc_box_seen) {
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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toposort.sort();
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log_assert(!toposort.found_loops);
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc_box_id"))
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continue;
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cell->connections_.sort(RTLIL::sort_by_id_str());
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input) {
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/*if (!w->port_input)*/ {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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/*if (!output_bits.count(b))*/
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co_bits.emplace_back(b, 0);
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}
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}
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if (is_output) {
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SigBit O = sigmap(b);
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/*if (!input_bits.count(O))*/
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ci_bits.emplace_back(O, 0);
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}
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}
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}
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box_list.emplace_back(cell);
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}
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if (abc_box)
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box_list.emplace_back(cell);
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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// TODO: Free memory from toposort, bit_drivers, bit_users
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}
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for (auto bit : input_bits) {
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@ -329,15 +391,15 @@ struct XAigerWriter
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aig_m++, aig_i++;
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}
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if (zinit_mode)
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{
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for (auto it : ff_map) {
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if (init_map.count(it.first))
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continue;
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aig_m++, aig_i++;
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init_inputs[it.first] = 2*aig_m;
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}
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}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map) {
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// if (init_map.count(it.first))
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// continue;
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// aig_m++, aig_i++;
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// init_inputs[it.first] = 2*aig_m;
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// }
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//}
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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@ -349,29 +411,29 @@ struct XAigerWriter
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aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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}
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if (!initstate_bits.empty() || !init_inputs.empty()) {
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aig_m++, aig_l++;
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initstate_ff = 2*aig_m+1;
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aig_latchinit.push_back(0);
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}
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//if (!initstate_bits.empty() || !init_inputs.empty()) {
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// aig_m++, aig_l++;
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// initstate_ff = 2*aig_m+1;
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// aig_latchinit.push_back(0);
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//}
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if (zinit_mode)
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{
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for (auto it : ff_map)
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{
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int l = ordered_latches[it.first];
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//if (zinit_mode)
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//{
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// for (auto it : ff_map)
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// {
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// int l = ordered_latches[it.first];
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if (aig_latchinit.at(l) == 1)
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aig_map[it.first] ^= 1;
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// if (aig_latchinit.at(l) == 1)
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// aig_map[it.first] ^= 1;
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if (aig_latchinit.at(l) == 2)
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{
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int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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}
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}
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}
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// if (aig_latchinit.at(l) == 2)
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// {
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// int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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// int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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// aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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// }
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// }
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//}
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for (auto it : ff_map) {
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int a = bit2aig(it.second);
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@ -382,8 +444,8 @@ struct XAigerWriter
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aig_latchin.push_back(a);
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}
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if (!initstate_bits.empty() || !init_inputs.empty())
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aig_latchin.push_back(1);
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//if (!initstate_bits.empty() || !init_inputs.empty())
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// aig_latchin.push_back(1);
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for (auto &c : co_bits) {
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RTLIL::SigBit bit = c.first;
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@ -518,14 +580,14 @@ struct XAigerWriter
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
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}
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if (init_inputs.count(sig[i])) {
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int a = init_inputs.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
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else
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
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}
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//if (init_inputs.count(sig[i])) {
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// int a = init_inputs.at(sig[i]);
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// log_assert((a & 1) == 0);
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// if (GetSize(wire) != 1)
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// symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
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// else
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// symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
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//}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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@ -687,12 +749,12 @@ struct XAigerWriter
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continue;
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}
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if (init_inputs.count(sig[i])) {
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int a = init_inputs.at(sig[i]);
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log_assert((a & 1) == 0);
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init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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continue;
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}
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//if (init_inputs.count(sig[i])) {
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// int a = init_inputs.at(sig[i]);
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// log_assert((a & 1) == 0);
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// init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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// continue;
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//}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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