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Code Activity
yosys/backends
History
Eddie Hung 3544a7cd7b ignore_boxes -> holes_mode
2019-04-19 08:37:10 -07:00
..
aiger ignore_boxes -> holes_mode 2019-04-19 08:37:10 -07:00
blif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
btor Add support for memory initialization to write_btor 2019-03-23 14:40:01 +01:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Refine memory support to deal with general Verilog memory definitions. 2019-04-01 15:02:12 -07:00
ilang Fix a syntax bug in ilang backend related to process case statements 2019-03-14 17:50:20 +01:00
intersynth Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
json write_json to not write contents (cells/wires) of whiteboxes 2019-04-18 10:30:45 -07:00
protobuf Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
simplec Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smt2 Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
smv Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00