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Author SHA1 Message Date
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller
3101b9b8c9 Fix remaining log_file_error(); emit dependent file references in new line. 
There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
 2018-07-20 18:52:52 -07:00
Clifford Wolf
323f6f6f60
Merge pull request #586 from hzeller/more-sourcepos-logging 
Convert more log_error() to log_file_error() where possible.
 2018-07-20 19:22:59 +02:00
Henner Zeller
68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Clifford Wolf
1de07eeee2
Merge pull request #585 from hzeller/use-file-warning-error 
Use log_file_warning(), log_file_error() functions
 2018-07-20 17:46:06 +02:00
Henner Zeller
b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Clifford Wolf
bf68e9a94a
Merge pull request #584 from hzeller/provide-source-location-logging 
Provide source-location logging.
 2018-07-20 16:36:06 +02:00
Henner Zeller
1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Clifford Wolf
87aef8f0cc Add async2sync pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-19 15:31:12 +02:00
Aman Goel
5dcb899e76
Merge pull request #2 from YosysHQ/master 
Merging with official repo
 2018-07-18 11:34:18 -04:00
Clifford Wolf
65234d4b24 Fix handling of eventually properties in verific importer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-17 12:43:30 +02:00
Clifford Wolf
5041ed2f7d Fix verific -vlog-incdir and -vlog-libdir handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 18:47:42 +02:00
Clifford Wolf
3b79a2e3dc
Merge pull request #581 from daveshah1/ecp5 
Adding ECP5 synthesis target
 2018-07-16 16:58:14 +02:00
Clifford Wolf
f897af626d Fix "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 16:48:09 +02:00
David Shah
3a3558acce ecp5: Fixing miscellaneous sim model issues 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:56:12 +02:00
Clifford Wolf
ee68b4d963 Merge branch 'master' of github.com:YosysHQ/yosys 2018-07-16 15:32:38 +02:00
Clifford Wolf
f39b897545 Add "read -incdir" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-16 15:32:26 +02:00
David Shah
e9ef077266 ecp5: Fixing 'X' issues with LUT simulation models 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:20:34 +02:00
David Shah
b2c62ff8ef ecp5: ECP5 synthesis fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 14:33:13 +02:00
David Shah
459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
David Shah
241429abac ecp5: Add DRAM match rule 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:25:52 +02:00
David Shah
4a60bc83ab ecp5: Cells and mappings fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:14:08 +02:00
David Shah
b0fea67cc6 ecp5: Fixing arith_map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:49:59 +02:00
David Shah
11c916840d ecp5: Initial arith_map implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:46:12 +02:00
David Shah
c2d7be140a ecp5: Adding basic synth_ecp5 based on synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4 ecp5: Adding DFF maps 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:32:23 +02:00
Clifford Wolf
db4514944d
Merge pull request #580 from daveshah1/ice40_nx 
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
 2018-07-13 14:31:38 +02:00
David Shah
1def34f2a6 ecp5: Adding DRAM map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94 ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3 ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:09:18 +02:00
Benedikt Tutzer
0371519c39 Added Monitor class that can monitor all changes in a Design or in a Module 2018-07-10 12:51:02 +02:00
Benedikt Tutzer
e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer
55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer
da8083dbd0 commands can now be run on arbitrary designs, not only on the active one 2018-07-09 16:01:56 +02:00
Benedikt Tutzer
8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
William D. Jones
0caa62802c Gate POSIX-only signals and resource module to only run on POSIX Python implementations. 2018-07-06 01:44:34 -04:00
Aman Goel
f0b1ec3e97 Merge branch 'YosysHQ-master' 2018-07-04 15:14:58 -04:00
Aman Goel
4d343fc1cd Merging with official repo 2018-07-04 15:14:28 -04:00
Clifford Wolf
8b92ddb9d2 Fix verific eventually handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:24:58 +02:00
Clifford Wolf
0404cf61d5 Add verific support for eventually properties 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 19:21:04 +02:00
Clifford Wolf
ebf0f003d3 Add "verific -formal" and "read -formal" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-29 10:02:27 +02:00
Clifford Wolf
afedb2d03e Add "read -sv -D" support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:58:15 +02:00
Clifford Wolf
07e616900c Add "read -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 23:43:38 +02:00
Clifford Wolf
fe2ee833e1 Fix handling of signed memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-28 16:57:03 +02:00
Benedikt Tutzer
7911379d4a Introduced namespace and removed class-prefixes to increase readability 2018-06-28 15:07:21 +02:00
Benedikt Tutzer
ccb4dcd013 changed references from hash-ids to IdString names 2018-06-28 14:44:28 +02:00
William D. Jones
7e5801beed Add support for 64-bit builds using msys2 environment. 2018-06-27 16:36:18 -04:00
William D. Jones
ee7164b879 Use msys2-provided pthreads instead of abc's. 2018-06-27 16:26:36 -04:00
Benedikt Tutzer
a27fa1833e added wrappers for Design, Modules, Cells and Wires 2018-06-25 17:08:29 +02:00
Clifford Wolf
848c3c5c88 Add YOSYS_NOVERIFIC env variable for temporarily disabling verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 20:40:22 +02:00