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	changed references from hash-ids to IdString names
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					 1 changed files with 32 additions and 64 deletions
				
			
		|  | @ -3,6 +3,11 @@ | |||
| #include "yosys.h" | ||||
| #include <boost/python.hpp> | ||||
| 
 | ||||
| struct YosysDesign; | ||||
| struct YosysModule; | ||||
| struct YosysCell; | ||||
| struct YosysWire; | ||||
| 
 | ||||
| void yosys_setup() | ||||
| { | ||||
| 	Yosys::log_streams.push_back(&std::cout); | ||||
|  | @ -24,16 +29,13 @@ void yosys_shutdown() | |||
| 
 | ||||
| struct YosysCell | ||||
| { | ||||
| 	unsigned int hashid; | ||||
| 
 | ||||
| 	YosysCell(unsigned int hashid) | ||||
| 	{ | ||||
| 		this->hashid = hashid; | ||||
| 	} | ||||
| 	Yosys::RTLIL::IdString name; | ||||
| 	Yosys::RTLIL::IdString parent_name; | ||||
| 
 | ||||
| 	YosysCell(Yosys::RTLIL::Cell* ref) | ||||
| 	{ | ||||
| 		this->hashid = ref->hashidx_; | ||||
| 		this->name = ref->name; | ||||
| 		this->parent_name = ref->module->name; | ||||
| 	} | ||||
| 	 | ||||
| 	Yosys::RTLIL::Cell* get_cpp_obj() | ||||
|  | @ -41,34 +43,27 @@ struct YosysCell | |||
| 		Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); | ||||
| 		if(active_design == NULL) | ||||
| 			return NULL; | ||||
| 		for(auto &mod_it : active_design->modules_) | ||||
| 		{ | ||||
| 			for(auto &cell_it : mod_it.second->cells_) | ||||
| 				if(cell_it.second->hashidx_ == this->hashid) | ||||
| 					return cell_it.second; | ||||
| 		} | ||||
| 		return NULL; | ||||
| 		if(active_design->modules_[this->parent_name] == NULL) | ||||
| 			return NULL; | ||||
| 		return active_design->modules_[this->parent_name]->cells_[this->name]; | ||||
| 	} | ||||
| }; | ||||
| 
 | ||||
| std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) | ||||
| { | ||||
| 	ostr << "Cell with id " << cell.hashid; | ||||
| 	ostr << "Cell with name " << cell.name.c_str(); | ||||
| 	return ostr; | ||||
| } | ||||
| 
 | ||||
| struct YosysWire | ||||
| { | ||||
| 	unsigned int hashid; | ||||
| 
 | ||||
| 	YosysWire(unsigned int hashid) | ||||
| 	{ | ||||
| 		this->hashid = hashid; | ||||
| 	} | ||||
| 	Yosys::RTLIL::IdString name; | ||||
| 	Yosys::RTLIL::IdString parent_name; | ||||
| 
 | ||||
| 	YosysWire(Yosys::RTLIL::Wire* ref) | ||||
| 	{ | ||||
| 		this->hashid = ref->hashidx_; | ||||
| 		this->name = ref->name; | ||||
| 		this->parent_name = ref->module->name; | ||||
| 	} | ||||
| 	 | ||||
| 	Yosys::RTLIL::Wire* get_cpp_obj() | ||||
|  | @ -76,35 +71,27 @@ struct YosysWire | |||
| 		Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); | ||||
| 		if(active_design == NULL) | ||||
| 			return NULL; | ||||
| 		for(auto &mod_it : active_design->modules_) | ||||
| 		{ | ||||
| 			for(auto &wire_it : mod_it.second->wires_) | ||||
| 				if(wire_it.second->hashidx_ == this->hashid) | ||||
| 					return wire_it.second; | ||||
| 		} | ||||
| 		return NULL; | ||||
| 		if(active_design->modules_[this->parent_name] == NULL) | ||||
| 			return NULL; | ||||
| 		return active_design->modules_[this->parent_name]->wires_[this->name]; | ||||
| 	} | ||||
| }; | ||||
| 
 | ||||
| std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) | ||||
| { | ||||
| 	ostr << "Wire with id " << wire.hashid; | ||||
| 	ostr << "Wire with name " << wire.name.c_str(); | ||||
| 	return ostr; | ||||
| } | ||||
| 
 | ||||
| 
 | ||||
| struct YosysModule | ||||
| { | ||||
| 	unsigned int hashid; | ||||
| 
 | ||||
| 	YosysModule(unsigned int hashid) | ||||
| 	{ | ||||
| 		this->hashid = hashid; | ||||
| 	} | ||||
| 	Yosys::RTLIL::IdString name; | ||||
| 	unsigned int parent_hashid; | ||||
| 
 | ||||
| 	YosysModule(Yosys::RTLIL::Module* ref) | ||||
| 	{ | ||||
| 		this->hashid = ref->hashidx_; | ||||
| 		this->name = ref->name; | ||||
| 		this->parent_hashid = ref->design->hashidx_; | ||||
| 	} | ||||
| 
 | ||||
| 	Yosys::RTLIL::Module* get_cpp_obj() | ||||
|  | @ -112,12 +99,9 @@ struct YosysModule | |||
| 		Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); | ||||
| 		if(active_design == NULL) | ||||
| 			return NULL; | ||||
| 		for(auto &mod_it : active_design->modules_) | ||||
| 		{ | ||||
| 			if(mod_it.second->hashidx_ == this->hashid) | ||||
| 				return mod_it.second; | ||||
| 		} | ||||
| 		return NULL; | ||||
| 		if(active_design->hashidx_ != this->parent_hashid) | ||||
| 			printf("Somehow the active design changed!\n"); | ||||
| 		return active_design->modules_[this->name]; | ||||
| 	} | ||||
| 
 | ||||
| 	boost::python::list get_cells() | ||||
|  | @ -149,7 +133,7 @@ struct YosysModule | |||
| 
 | ||||
| std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) | ||||
| { | ||||
| 	ostr << "Module with id " << module.hashid; | ||||
| 	ostr << "Module with name " << module.name.c_str(); | ||||
| 	return ostr; | ||||
| } | ||||
| 
 | ||||
|  | @ -169,22 +153,6 @@ struct YosysDesign | |||
| 		{ | ||||
| 			printf("design is not null and has id %u\n", active_design->hashidx_); | ||||
| 			this->hashid = active_design->hashidx_; | ||||
| 			/*
 | ||||
| 			for (auto &mod_it : active_design->modules_) | ||||
| 			{ | ||||
| 				printf("found module in design!!!\n"); | ||||
| 				//design->add(it.second->clone());
 | ||||
| 				 | ||||
| 				for (auto &wire_it : mod_it.second->wires_) | ||||
| 				{ | ||||
| 					printf("found wire in module!!!\n"); | ||||
| 				} | ||||
| 
 | ||||
| 				for (auto &cell_it : mod_it.second->cells_) | ||||
| 				{ | ||||
| 					printf("found cell in module!!!\n"); | ||||
| 				} | ||||
| 			}*/ | ||||
| 		} | ||||
| 	} | ||||
| 
 | ||||
|  | @ -217,19 +185,19 @@ BOOST_PYTHON_MODULE(libyosys) | |||
| 		.def("get_modules", &YosysDesign::get_modules) | ||||
| 		; | ||||
| 
 | ||||
| 	class_<YosysModule>("YosysModule", init<unsigned int>()) | ||||
| 	class_<YosysModule>("YosysModule", no_init) | ||||
| 		.def(boost::python::self_ns::str(boost::python::self_ns::self)) | ||||
| 		.def(boost::python::self_ns::repr(boost::python::self_ns::self)) | ||||
| 		.def("get_cells", &YosysModule::get_cells) | ||||
| 		.def("get_wires", &YosysModule::get_wires) | ||||
| 		; | ||||
| 
 | ||||
| 	class_<YosysCell>("YosysCell", init<unsigned int>()) | ||||
| 	class_<YosysCell>("YosysCell", no_init) | ||||
| 		.def(boost::python::self_ns::str(boost::python::self_ns::self)) | ||||
| 		.def(boost::python::self_ns::repr(boost::python::self_ns::self)) | ||||
| 		; | ||||
| 
 | ||||
| 	class_<YosysWire>("YosysWire", init<unsigned int>()) | ||||
| 	class_<YosysWire>("YosysWire", no_init) | ||||
| 		.def(boost::python::self_ns::str(boost::python::self_ns::self)) | ||||
| 		.def(boost::python::self_ns::repr(boost::python::self_ns::self)) | ||||
| 		; | ||||
|  |  | |||
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