mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
9264 commits 123 branches 59 tags 44 MiB
Commit graph

3094 commits

Author SHA1 Message Date
Eddie Hung
1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Miodrag Milanovic
5641b0248f Option to expect no warnings 2020-02-17 15:36:06 +01:00
R. Ou
fec7dc5c9e extract_counter: Implement extracting up counters 2020-02-17 03:08:52 -08:00
R. Ou
940bab6841 extract_counter: Add support for inverted clock enable 2020-02-17 03:08:52 -08:00
R. Ou
5fc180ed2d extract_counter: Fix clock enable 2020-02-17 03:08:52 -08:00
R. Ou
12fa4a3121 extract_counter: Fix outputting count to module port 2020-02-17 03:08:52 -08:00
R. Ou
508f1ff6a1 extract_counter: Allow forbidding async reset 2020-02-17 03:08:52 -08:00
R. Ou
7b922c0d89 extract_counter: Refactor out extraction settings into struct 2020-02-17 03:08:52 -08:00
Tim 'mithro' Ansell
b9dfdbbfee show: Add -nobg argument. 
Makes yosys wait for the viewer command to finish before continuing.
 2020-02-15 14:03:16 +01:00
Eddie Hung
f9f86fd758 Revert "abc9: fix abc9_arrival for flops" 
This reverts commit f7c0dbecee.
 2020-02-14 16:08:04 -08:00
Miodrag Milanovic
31b7a9c312 Add expect option to logger command 2020-02-14 12:21:16 +01:00
Eddie Hung
0cf7598cd6
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes 
Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
 2020-02-13 17:32:54 -08:00
Eddie Hung
3d2a2e8799 iopadmap: fixes as suggested by @mwkmwkmwk 2020-02-13 14:57:06 -08:00
Eddie Hung
f7c0dbecee abc9: fix abc9_arrival for flops 2020-02-13 12:34:09 -08:00
Eddie Hung
00d41905df abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
Eddie Hung
ebb11bcea4 iopadmap: move \init attributes from outpad output to its input 2020-02-13 12:05:14 -08:00
Miodrag Milanovic
0ba2a2b1fa Add new logger pass 2020-02-13 13:35:29 +01:00
Eddie Hung
c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung
e6bb7b0782 Fix misc.abc9.abc9_abc9_luts 2020-02-07 08:27:45 -08:00
whitequark
60f047f136 memory_bram: add attr_icase option. 
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
 2020-02-06 14:58:20 +00:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 
opt_merge: discard \init of '$' cells with 'Q' port when merging
 2020-02-05 14:56:26 -08:00
Eddie Hung
0b308c6835 abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631 
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
 2020-02-05 19:31:18 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
David Shah
4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 
synth_xilinx: add -dsp-multonly
 2020-02-02 14:53:32 +00:00
David Shah
65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Eddie Hung
136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Gabriel Somlo
8106c3d31b abc9: restore ability to use ABCEXTERNAL 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-01-30 15:12:43 -05:00
Claire Wolf
1679682fa3 Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys 
Also some minor fixes to the original PR.
 2020-01-29 17:01:24 +01:00
Claire Wolf
4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check 
opt_reduce: Call check() per run rather than per optimised cell
 2020-01-29 15:27:11 +01:00
Eddie Hung
a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
David Shah
6fd9cae5ca opt_reduce: Call check() per run rather than per optimised cell 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-28 09:42:01 +00:00
Pepijn de Vos
409e532433 redirect fuser stderr to /dev/null 2020-01-28 10:02:41 +01:00
Eddie Hung
21ce1b37fb abc9_ops: -check for negative arrival/required times 2020-01-27 14:22:46 -08:00
Eddie Hung
e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Eddie Hung
9009b76a69 abc9_ops: add comments 2020-01-27 11:18:21 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
dbf351390e abc9: -reintegrate recover type from existing cell, check against boxid 2020-01-23 22:45:34 -08:00
Eddie Hung
245873d42d abc9: warning message if no modules selected 2020-01-23 19:08:51 -08:00
Eddie Hung
f180dba753 abc9_ops: -prep_xaiger to skip (* keep *) cells 2020-01-23 18:56:06 -08:00
Eddie Hung
1d4314d888 abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_* 2020-01-23 14:58:56 -08:00