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16830 commits 124 branches 65 tags 59 MiB
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2421 commits

Author SHA1 Message Date
nella
a54c0149bf Convert bram tests 2026-03-20 16:32:46 +01:00
nella
e7cc04954d Convert memfile tests 2026-03-20 16:32:46 +01:00
nella
ca77e0a5db Convert memlib tests 2026-03-20 16:32:46 +01:00
Miodrag Milanovic
0297eabeb3 Make test simple 2026-03-20 16:16:58 +01:00
Miodrag Milanovic
323747e3de Better fix 2026-03-20 15:38:24 +01:00
Miodrag Milanovic
4ff4af7389 Try fixing tests 2026-03-20 15:12:51 +01:00
Miodrag Milanovic
799c07a126 Did share, opt_share and fsm 2026-03-20 12:47:15 +01:00
Miodrag Milanovic
2b10385edd Convert xprop tests 2026-03-18 15:25:28 +01:00
Miodrag Milanovic
de8b6286b8 Converted some more 2026-03-18 09:54:33 +01:00
Miodrag Milanovic
d0ac6d9791 Converted blif tests 2026-03-18 09:45:33 +01:00
Miodrag Milanovic
92bdccf2be Convert memories tests 2026-03-18 08:46:58 +01:00
Miodrag Milanovic
77147fb0db Correctly handle errors 2026-03-18 08:46:34 +01:00
Miodrag Milanovic
fa92d22660 Document not covered 2026-03-16 15:45:59 +01:00
Miodrag Milanovic
488f144245 Convert autotest script wrapper 2026-03-16 13:07:11 +01:00
Miodrag Milanovic
896fac04ed cleanup 2026-03-16 10:48:10 +01:00
Miodrag Milanovic
af3a53720c Use generic testing on few more places 2026-03-16 10:13:10 +01:00
Miodrag Milanovic
80fff7ce09 cleanup 2026-03-13 11:18:03 +01:00
Miodrag Milanovic
f2e1ac23a2 add prep 2026-03-13 11:15:21 +01:00
Miodrag Milanovic
413b9a4639 Add common.mk 2026-03-13 11:00:08 +01:00
Miodrag Milanovic
144da16583 report on summary 2026-03-13 10:15:17 +01:00
Miodrag Milanovic
903c74e42b Look for all result files 2026-03-13 10:10:34 +01:00
Miodrag Milanovic
f9cd49f7b9 Save results, and create summary and report 2026-03-13 09:51:15 +01:00
Miodrag Milanovic
2fb0ca49ff Convert gen-tests shell script to python 2026-03-13 08:38:05 +01:00
Miodrag Milanovic
486c3715fb Enabled realmath that was disabled for some reason 2026-03-11 08:02:11 +01:00
Miodrag Milanovic
2123121d23 Fix deprecation warning 2026-03-10 16:15:07 +01:00
Miodrag Milanovic
8a6954413f Clean some seed-tests outputs 2026-03-10 15:57:24 +01:00
Miodrag Milanovic
ede782d7e3 Clean some seed-tests outputs 2026-03-10 11:50:30 +01:00
Miodrag Milanovic
a155994868 Cleanup for abcopt-tests 2026-03-10 11:18:05 +01:00
Miodrag Milanovic
169b9994dc Ignore some generated files 2026-03-10 11:05:47 +01:00
Miodrag Milanovic
c08a2aa3ff Do not write to console for makefile-tests 2026-03-10 11:02:20 +01:00
Miodrag Milanovic
1a864c72ae Make sure targets are built for tests 2026-03-10 10:08:52 +01:00
Miodrag Milanovic
108a9133d0 Move clean for tests in proper Makefile 2026-03-10 10:01:23 +01:00
Miodrag Milanovic
92ef719434 Split vanilla-test to separate Makefile 2026-03-10 09:41:39 +01:00
Lofty
050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic
602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic
52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Lofty
cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Lofty
39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Andrew Pullin
6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella
b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b newcelltypes: extend testing 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955 pyosys: disable test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
f594014bef newcelltypes: proper bounds for unit test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
d91e1c8607 newcelltypes: test against builtin_ff_cell_types 2026-03-04 12:22:14 +01:00