1822 commits

Author	SHA1	Message	Date
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00
Clifford Wolf	cdb6ceb8c6	Add support for verific mem initialization	2017-02-11 15:57:36 +01:00
Clifford Wolf	c449f4b86f	Fix another stupid bug in the same line	2017-02-11 11:47:51 +01:00
Clifford Wolf	fa4a7efe15	Add verific support for initialized variables	2017-02-11 11:40:18 +01:00
Clifford Wolf	0b7aac645c	Improve handling of Verific warnings and error messages	2017-02-11 11:39:50 +01:00
Clifford Wolf	eb7b18e897	Fix extremely stupid typo	2017-02-11 11:09:07 +01:00
Clifford Wolf	848062088c	Add checker support to verilog front-end	2017-02-09 13:51:44 +01:00
Clifford Wolf	2ca8d483dd	Add "rand" and "rand const" verific support	2017-02-09 12:53:46 +01:00
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	1d1f56a361	Add PSL parser mode to verific front-end	2017-02-08 10:40:33 +01:00
Clifford Wolf	7e0b776a79	Add "read_blif -wideports"	2017-02-06 14:48:03 +01:00
Clifford Wolf	6abf79eb28	Further improve cover() support	2017-02-04 17:02:13 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	911c44d164	Add assert/assume support to verific front-end	2017-02-04 13:36:00 +01:00
Clifford Wolf	fea528280b	Add "enum" and "typedef" lexer support	2017-01-17 17:33:52 +01:00
Clifford Wolf	78f65f89ff	Fix bug in AstNode::mem2reg_as_needed_pass2()	2017-01-15 13:52:50 +01:00
Clifford Wolf	2d32c6c4f6	Fixed handling of local memories in functions	2017-01-05 13:19:03 +01:00
Clifford Wolf	81a9ee2360	Added handling of local memories and error for local decls in unnamed blocks	2017-01-04 16:03:04 +01:00
Clifford Wolf	dfb461fe52	Added Verilog $rtoi and $itor support	2017-01-03 17:40:58 +01:00
Clifford Wolf	3886669ab6	Added "verilog_defines" command	2016-12-15 17:49:28 +01:00
Clifford Wolf	ecdc22b06c	Added support for macros as include file names	2016-11-28 14:50:17 +01:00
Clifford Wolf	c7f6fb6e17	Bugfix in "read_verilog -D NAME=VAL" handling	2016-11-28 14:45:05 +01:00
Clifford Wolf	70d7a02cae	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
Clifford Wolf	a926a6afc2	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
Clifford Wolf	2874914bcb	Fixed anonymous genblock object names	2016-11-04 07:46:30 +01:00
Clifford Wolf	56e2bb88ae	Some fixes in handling of signed arrays	2016-11-01 23:17:43 +01:00
Clifford Wolf	aa72262330	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
Clifford Wolf	042b67f024	No limit for length of lines in BLIF front-end	2016-10-19 12:44:58 +02:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	8f5bf6de32	Added liberty parser support for types within cell decls	2016-09-23 13:53:23 +02:00
Clifford Wolf	aaa99c35bd	Added $past, $stable, $rose, $fell SVA functions	2016-09-19 01:30:07 +02:00
Clifford Wolf	13a03b84d4	Added support for bus interfaces to "read_liberty -lib"	2016-09-18 18:48:59 +02:00
Clifford Wolf	ab18e9df7c	Added assertpmux	2016-09-07 00:28:01 +02:00
Clifford Wolf	d55a93b39f	Bugfix in parsing of BLIF latch init values	2016-09-06 17:35:06 +02:00
Clifford Wolf	97583ab729	Avoid creation of bogus initial blocks for assert/assume in always @*	2016-09-06 17:34:42 +02:00
Clifford Wolf	aa25a4cec6	Added $anyconst support to yosys-smtbmc	2016-08-30 19:27:42 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	1276c87a56	Added read_verilog -norestrict -assume-asserts	2016-08-26 23:35:27 +02:00
Clifford Wolf	4be4969bae	Improved verilog parser errors	2016-08-25 11:44:37 +02:00
Clifford Wolf	cd18235f30	Added SV "restrict" keyword	2016-08-24 15:30:08 +02:00
Clifford Wolf	450f6f59b4	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
Clifford Wolf	82a4a0230f	Another bugfix in mem2reg code	2016-08-21 13:23:58 +02:00
Clifford Wolf	dbdd8927e7	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	2016-08-21 13:18:09 +02:00
Clifford Wolf	fe9315b7a1	Fixed finish_addr handling in $readmemh/$readmemb	2016-08-20 13:47:46 +02:00
Clifford Wolf	f6629b9c29	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
Clifford Wolf	e9fe57c75e	Only allow posedge/negedge with 1 bit wide signals	2016-08-10 19:32:11 +02:00
Clifford Wolf	7f755dec75	Fixed bug in parsing real constants	2016-08-06 13:16:23 +02:00