Krystine Sherwin
829e02ec5b
Docs: Shorten cmd:ref
2024-10-15 07:22:04 +13:00
Akash Levy
469f5a707a
Merge branch 'YosysHQ:main' into main
2024-10-14 11:21:54 -07:00
Krystine Sherwin
e4ec3717bc
Docs: Update internal cells to autoref
2024-10-15 07:18:28 +13:00
Krystine Sherwin
c0f9828b3c
Docs: Add autoref role
...
Use new `autoref` role when using single backticks. Allows automatic mapping to a cmd ref or a cell ref.
2024-10-15 07:17:36 +13:00
Krystine Sherwin
f9b4e04fef
Docs: Add cell reference
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Subclass the command reference code in order to support smart references to the internal cells.
2024-10-15 07:17:36 +13:00
Krystine Sherwin
c98d134662
cellhelp: Extra newline
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Fix `$macc` page.
2024-10-15 07:17:35 +13:00
Krystine Sherwin
d629aa6bf1
cellhelp: Split gate-level and word-level cells
2024-10-15 07:17:35 +13:00
Krystine Sherwin
1a4ada40fe
Docs: Add cell gen to makefile
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Generate in a temp directory and use `rsync -rc` to only update rst files that have changed. This prevents sphinx from having to re-generate every cmd/cell page any time the git sha changes.
Also change cmd gen to match.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
57cd8d29db
cellhelp: Add default format parse for simcells
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Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
a2b2904ed8
cellhelp: Add source line to help
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Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
784292626e
cellhelp: Rename short_desc to title
2024-10-15 07:16:39 +13:00
Krystine Sherwin
1e5a50ff3a
Docs: Convert write_cell_rst to use SimHelper
2024-10-15 07:16:39 +13:00
Krystine Sherwin
4662476ec8
Docs: Test $alu with v2 help format
2024-10-15 07:16:39 +13:00
Krystine Sherwin
600149a824
Docs: Add back message for empty help
2024-10-15 07:16:39 +13:00
Krystine Sherwin
6bbe763845
Docs: Put cell library help strings into a struct
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Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
2024-10-15 07:16:39 +13:00
Krystine Sherwin
a6641da73c
Docs: Initial version of cell_ref autogen
2024-10-15 07:16:39 +13:00
Akash Levy
0d5aa5bb77
Update Makefile to include sat
2024-10-14 09:57:56 -07:00
Emil J
1113b88cb2
Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json
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synth_xilinx: add -json
2024-10-14 06:45:14 -07:00
Emil J
caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip
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Represent string constants as strings
2024-10-14 06:42:54 -07:00
N. Engelhardt
518b6aec36
Merge pull request #4654 from YosysHQ/micko/vhdl_assert
2024-10-14 15:05:22 +02:00
Emil J. Tywoniak
bc5d9d1bd3
functional: fix std::move usage in Factory::constant
2024-10-14 06:28:14 +02:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Akash Levy
f4de53120e
Bump dep
2024-10-13 11:01:54 -07:00
Akash Levy
8e6ac65dd8
Merge branch 'YosysHQ:main' into main
2024-10-13 10:59:19 -07:00
Emil J
61ed9b6263
Merge pull request #4608 from phsauter/rtlil-const-compress
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rtlil: add Const::compress helper function
2024-10-12 20:38:25 -07:00
github-actions[bot]
7f2bf3170f
Bump version
2024-10-13 00:22:25 +00:00
Jean-François Nguyen
f953a516d0
cxxrtl: fix handling of 0-bit variables in vcd_writer.sample().
2024-10-13 01:00:40 +01:00
Akash Levy
d5ff6b4873
Update yosys-slang dep
2024-10-12 16:03:51 -07:00
Akash Levy
db95ed6c77
Merge branch 'YosysHQ:main' into main
2024-10-12 16:02:50 -07:00
Robin Ole Heinemann
0f762f75a6
cxxrtl: fix vcd writer scope handling
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The vcd writer incorrectly treated two scope vectors as the same, whenever
they have the same length of entries and the last item matches.
This is however not always true, for example consider a current_scope of
["top", "something0", "same"]
and a scope of
["top", "something1", "same"]
2024-10-12 14:41:53 +01:00
Miodrag Milanović
a8f4bc2904
Merge pull request #4659 from YosysHQ/emil/cxxopts-https
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cxxopts: https submodule
2024-10-12 14:07:01 +02:00
Emil J. Tywoniak
999d1f40bc
cxxopts: https submodule
2024-10-12 10:32:09 +02:00
Emil J
5c9b2df689
Merge pull request #4616 from YosysHQ/emil/cxxopts
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driver: replace getopt with cxxopts, replace -B, clean up help
2024-10-12 00:52:34 -07:00
Akash Levy
eae66c7d6a
Update deps
2024-10-11 15:49:42 -07:00
Akash Levy
bf4b7ec0ea
Merge branch 'YosysHQ:main' into main
2024-10-11 15:40:49 -07:00
Miodrag Milanovic
8d2b63bb8a
Set VHDL assert condition initial state if fed by FF
2024-10-11 16:32:21 +02:00
Martin Povišer
a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut
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cellmatch: Size the `lut` attribute
2024-10-11 14:08:55 +02:00
Akash Levy
fe19e2e179
Update yosys-slang
2024-10-10 23:15:38 -07:00
Akash Levy
71d672ebe9
Fix muxadd peepopt
2024-10-10 13:35:14 -07:00
Akash Levy
4dfe7ec750
Update yosys-slang dep
2024-10-10 13:35:01 -07:00
Akash Levy
6725f2d646
Move init_share_dirname to after Python is initialized
2024-10-10 13:34:39 -07:00
Akash Levy
48cb802599
Undo bound removal
2024-10-10 13:34:18 -07:00
Akash Levy
4334792d0c
Update gitignore
2024-10-10 13:34:05 -07:00
Akash Levy
b0b89627ac
Disable broken test
2024-10-10 13:31:59 -07:00
Akash Levy
ea4f153b42
Merge branch 'YosysHQ:main' into main
2024-10-10 10:24:07 -07:00
github-actions[bot]
0200a7680a
Bump version
2024-10-10 00:20:21 +00:00
Akash Levy
0ac341acf2
Merge latest and update yosys-slang dep
2024-10-09 15:34:02 -07:00
Philippe Sauter
c53c87e1f4
rtlil: add Const:: as_int_compressed function
2024-10-09 19:48:57 +02:00
Philippe Sauter
07fb8af05b
rtlil: handle all-zeros case in Const::compress
2024-10-09 19:48:57 +02:00
Philippe Sauter
4cd2e04da4
rtlil: add Const::compress helper function
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Compresses the current bits to the minimum
width representation by removing leading bits.
2024-10-09 19:48:57 +02:00
