mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

cellhelp: Extra newline

Browse source 
Fix `$macc` page.
This commit is contained in:
Krystine Sherwin 2024-05-03 09:23:54 +12:00
parent d629aa6bf1
commit c98d134662
No known key found for this signature in database
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/register.cc
View file

@ -900,7 +900,7 @@ struct HelpPass : public Pass {
fprintf(f, "%s\n", underline.c_str());
// help text
fprintf(f, "%s\n", cell.desc.c_str());
fprintf(f, "%s\n\n", cell.desc.c_str());
// source code
fprintf(f, "Simulation model (Verilog)\n");