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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-10-11 15:40:49 -07:00 • committed by GitHub
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passes/techmap/cellmatch.cc
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@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
for (auto bit : outputs) {
log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++];
bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
}
}