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Merge branch 'YosysHQ:main' into main
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commit
bf4b7ec0ea
1 changed files with 1 additions and 1 deletions
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@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
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for (auto bit : outputs) {
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log_assert(bit.is_wire());
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bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
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bit.wire->attributes[ID(lut)] = luts[no++];
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bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
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}
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}
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