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Code Activity
7946 commits 99 branches 53 tags 47 MiB
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247 commits

Author SHA1 Message Date
Clifford Wolf
fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Eddie Hung
29a8d4745e Cleanup synth_xilinx 2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a Working 2019-03-15 19:13:40 -07:00
Eddie Hung
af5706c2a3 Misspell 2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab Revert "Add shregmap -init_msb_first and use in synth_xilinx" 
This reverts commit 26ecbc1aee.
 2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee Add shregmap -init_msb_first and use in synth_xilinx 2019-03-14 08:10:02 -07:00
Eddie Hung
edca2f1163 Move shregmap until after first techmap 2019-03-13 17:13:52 -07:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf
13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Keith Rothman
5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Eddie Hung
fe4d6898de synth_xilinx to call shregmap with enable support 2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0 synth_xilinx to use shregmap with -params too 2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a synth_xilinx to now have shregmap call after dff2dffe 2019-02-28 09:32:29 -08:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Tim 'mithro' Ansell
b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Tim 'mithro' Ansell
d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf
6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf
a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf
17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf
864808992b Bugfix in Xilinx LUT mapping 2015-10-30 13:58:03 +01:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf
b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf
4389d9306e Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
Clifford Wolf
c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf
4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf
bebbf2e5a4 no support for 6-series xilinx devices 2015-02-01 23:06:44 +01:00
Clifford Wolf
816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf
d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf
279a18c9a3 Added synth_xilinx -retime -flatten 2015-01-17 20:47:18 +01:00
Clifford Wolf
7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf
dff8bd3b2a Added dff2dffe to synth_xilinx 2015-01-16 15:49:15 +01:00
Clifford Wolf
b197279f3c Added Xilinx MUXF7 and MUXF8 support 2015-01-15 13:50:04 +01:00
Clifford Wolf
153d3dd4e0 Various cleanups in synth_xilinx command 2015-01-13 13:20:32 +01:00
Clifford Wolf
4a0b3a5423 Various small improvements to synth_xilinx 2015-01-06 14:37:50 +01:00
Clifford Wolf
9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
20175afd29 Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
Clifford Wolf
4a3669d871 Added synth_xilinx command 2013-10-27 09:51:06 +01:00