synth_gowin guarded the mul2dsp + dsp_map path to gw1n/gw2a, so GW5A
multiplies expanded to LUTs. Add a gw5a branch mapping the GW5A's three
multiplier widths: $__MUL27X18 (M0 27x18) for larger multiplies, $__MUL12X12
(M1 12x12) for <=12x12 (which pack two-per-block via M0+M1), and $__MUL27X36
(27x36) for wide (B>18) multiplies.
The blocks are signed-only (no per-operand sign control), so DSP_SIGNEDONLY
is mandatory without it a 32x16 -1*-1 mapping yields 0x08000001 instead of 1.
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
- functions that have a const `[]` operator method now support `__getitem__` in Python
- fields of a pointer type now return a `reference_internal` instead of a `copy` because classes referenced to by pointers typically aren't copyable (e.g. RTLIL::Wire, RTLIL::Module, etc)
- removed duplicate of test_script.py
