114 commits

Author	SHA1	Message	Date
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	3b52121d32	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	3345fa0bab	Little steps in realmath test bench	2014-06-21 21:43:04 +02:00
Clifford Wolf	df76da8fd7	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:49:59 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	88470283c9	Little steps in realmath test bench	2014-06-16 15:21:08 +02:00
Clifford Wolf	398482eced	Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)	2014-06-15 09:39:22 +02:00
Clifford Wolf	a4ec19c25c	Added tests/realmath to "make test"	2014-06-15 09:31:03 +02:00
Clifford Wolf	656685fa31	Improved realmath test bench	2014-06-15 08:48:41 +02:00
Clifford Wolf	11d2add1b9	improved realmath test bench	2014-06-14 21:00:51 +02:00
Clifford Wolf	39eb347c67	progress in realmath test bench	2014-06-14 19:56:22 +02:00
Clifford Wolf	ebe2d73330	added first draft of real math testcase generator	2014-06-14 19:24:01 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	406f86a91e	Added realexpr.v test case	2014-06-14 12:01:17 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	3af7c69d1e	added tests for new verilog features	2014-06-07 12:26:11 +02:00
Clifford Wolf	c82db39935	Added tests/simple/repwhile.v	2014-06-06 17:47:20 +02:00
Clifford Wolf	a67cd2d4a2	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
Clifford Wolf	0ac915a757	Progress in Verific bindings	2014-03-14 11:46:13 +01:00
Clifford Wolf	bada3ee815	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	2014-03-11 11:59:58 +01:00
Clifford Wolf	4fd1a4c12b	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	2014-03-11 11:39:30 +01:00
Clifford Wolf	3c5e973092	Use private namespace in mem_simple_4x1_map	2014-02-21 12:14:38 +01:00
Clifford Wolf	81b3f52519	Added tests/techmap/mem_simple_4x1	2014-02-21 12:06:40 +01:00
Clifford Wolf	772330608a	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	2014-02-19 12:40:49 +01:00
Clifford Wolf	30379ea20d	Added frontend (-f) option to autotest.sh	2014-02-15 15:40:17 +01:00
Clifford Wolf	7664f5d92b	Updated ABC and some related changes	2014-02-13 08:07:08 +01:00
Clifford Wolf	9ce7b0fc3b	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	2014-02-12 13:11:58 +01:00
Clifford Wolf	039bb456cc	Added test cases for expose -evert-dff	2014-02-08 21:31:56 +01:00
Clifford Wolf	244e8ce1f4	Added splice command	2014-02-07 20:30:56 +01:00
Clifford Wolf	849fd62cfe	Added counters sat test case	2014-02-06 01:00:56 +01:00
Clifford Wolf	aa9da46807	Removed old unused files from tests/	2014-02-05 01:55:39 +01:00
Clifford Wolf	7a66b38c3e	Added test cases for sat command	2014-02-04 13:43:34 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	de9226a64f	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	2014-02-03 13:00:55 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	6dec0e0b3e	Added autotest.sh -p option	2014-01-02 17:52:48 +01:00
Clifford Wolf	ab3f6266ad	Use "abc -dff" in "make test"	2013-12-31 21:25:34 +01:00
Clifford Wolf	a582b9d184	Fixed commented out techmap call in tests/tools/autotest.sh	2013-12-31 13:51:25 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	994c83db01	Added multiplier test case from eda playground	2013-12-18 13:43:53 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	a2d053694b	Fix in sincos testbench gen	2013-12-04 09:24:52 +01:00
Clifford Wolf	d1517b7982	Added sincos test case	2013-12-04 09:10:41 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00