mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Fix in sincos testbench gen

Browse source
This commit is contained in:
Clifford Wolf 2013-12-04 09:24:52 +01:00
parent d1517b7982
commit a2d053694b
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/simple/sincos.v
View file

@ -39,7 +39,7 @@ input start;
input clock;
input reset;
(* gentb_constant="0" *)
(* gentb_constant = 1'b0 *)
wire reset;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR