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1750 commits

Author SHA1 Message Date
Akash Levy
71586d39b0 Merge from upstream 2025-11-12 08:14:33 -08:00
Robert O'Callahan
c4c389fdd7 Fix verilog backend to avoid IdString::c_str() 2025-11-12 11:52:04 +01:00
Akash Levy
950c619569 Smallfixes 2025-11-11 23:50:04 -08:00
Akash Levy
e21324d609 Merge from upstream 2025-11-11 22:52:11 -08:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
Handle unsized params
2025-11-12 07:14:44 +13:00
Robert O'Callahan
92ea557979 Build a temporary SigChunk list in the iterator in the cases where that's needed 2025-11-07 15:54:55 +00:00
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
Akash Levy
11731c91f4 Merge from upstream 2025-11-04 22:20:34 -08:00
KrystalDelusion
52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor
Refactor getting dirs and filenames from paths to files
2025-11-05 09:12:54 +13:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Emil J. Tywoniak
5cfe6a9c1e reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
Krystine Sherwin
1a0b5d8ea7 write_btor: Include $assert and $assume cells in -ywmap output 2025-10-09 14:50:36 +02:00
Akash Levy
16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Jannis Harder
90669ab4eb aiger2: Only fail for reachable undirected bufnorm helper cells
The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.

Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.

With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
2025-09-29 08:21:28 +02:00
Akash Levy
652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Robert O'Callahan
1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Akash Levy
d16ca47549
Merge branch 'YosysHQ:main' into main 2025-09-22 17:47:23 -07:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
Akash Levy
60d969530b Bump to latest 2025-09-21 01:10:04 -07:00
Jannis Harder
79e05a195d verilog: Bufnorm cell backend and frontend support
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Jannis Harder
47b3ee8c8b write_aiger2: Ignore the $input_port cell during indexing.
The $input_port cell is added by the bufnorm code to simplify handling
of input ports for new code that uses bufnorm, but the aiger2 backend
does already handle input ports separately, so we just ignore those.
2025-09-17 13:56:46 +02:00
Jannis Harder
4918f37be3 write_aiger2: Treat inout ports as output ports
With the previous bufnorm implementation inout ports were not supported
at all, so this didn't matter, but with the new bufnorm implementation
they need to be treated as output ports.
2025-09-17 13:56:46 +02:00
Jannis Harder
6466b15367
Merge pull request #5351 from jix/xaiger_ponum_fix
write_xaiger2: Fix output port mapping when opaque boxes are present
2025-09-17 13:56:21 +02:00
Jannis Harder
2d81726459 write_xaiger2: Fix output port mapping when opaque boxes are present 2025-09-17 13:10:04 +02:00
Emil J
73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff
Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
2025-09-17 11:37:16 +02:00
Robert O'Callahan
d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Robert O'Callahan
f80be49fa1 Remove unnecessary .c_str() in EDIF_ macros 2025-09-16 23:14:11 +00:00
Robert O'Callahan
a1141f1a4c Remove some unnecessary .c_str() calls to the result of unescape_id() 2025-09-16 23:12:14 +00:00
Robert O'Callahan
a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan
5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak
bcc69d5f6e write_rtlil: add -sort to match old behavior 2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
1328a33e82 write_rtlil: dump in insertion order 2025-09-16 15:47:14 +02:00
Emil J. Tywoniak
430adb3b59 write_rtlil: don't sort 2025-09-16 15:39:12 +02:00
Robert O'Callahan
34df6569a6 Update backends to avoid bits() 2025-09-16 03:17:23 +00:00
Akash Levy
f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Jannis Harder
193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion
More varargs conversion
2025-09-12 18:09:42 +02:00
Robert O'Callahan
ff5177ce8e Remove .c_str() from parameters to btorf() and infof() 2025-09-12 05:53:59 +00:00
Robert O'Callahan
6f0c8f56a3 Convert btorf()/infof() to C++ stringf machinery 2025-09-12 05:53:19 +00:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Akash Levy
a43de44f9d Merge upstream changes 2025-09-10 23:02:15 -07:00
Robert O'Callahan
d34ac0c87d Make log() use the FmtString infrastructure.
Now `log()` supports `std::string`.

We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
2025-09-09 15:41:03 +02:00
Akash Levy
1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Akash Levy
8204fd1d0b Update Yosys to latest 2025-09-06 16:49:39 -07:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Jannis Harder
41452e43b2
Merge pull request #4475 from georgerennie/skip_cover
smtbmc: Support skipping steps in cover mode
2025-09-01 13:53:04 +02:00
Jannis Harder
501bf4ce40
Merge pull request #4711 from georgerennie/george/btor_buf
write_btor: support $buf
2025-09-01 13:38:25 +02:00
Akash Levy
e54fa487b8 Merge from upstream 2025-08-21 17:56:55 -07:00
Robert O'Callahan
e0e70d1158 Remove some c_str() calls where they're no longer needed as parameters to stringf(). 2025-08-18 14:20:31 +01:00
Akash Levy
3733ad3879
Merge branch 'YosysHQ:main' into main 2025-08-11 09:26:32 -07:00
Hongce Zhang
76e507f307 update verilog_backend according to Github comments 2025-08-08 16:17:37 +08:00