mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-15 14:11:29 +00:00
Code Activity

Remove .c_str() calls from log()/log_error()

Browse source 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/aiger/aiger.cc
View file

@ -1040,7 +1040,7 @@ struct AigerBackend : public Backend {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
writer.write_map(mapf, verbose_map, no_startoffset);
}
@ -1051,7 +1051,7 @@ struct AigerBackend : public Backend {
PrettyJson json;
if (!json.write_to_file(yw_map_filename))
log_error("Can't open file `%s' for writing: %s\n", yw_map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", yw_map_filename, strerror(errno));
writer.write_ywmap(json);
}
}

2
backends/aiger/xaiger.cc
View file

@ -788,7 +788,7 @@ struct XAigerBackend : public Backend {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
writer.write_map(mapf);
}
}

2
backends/blif/blif.cc
View file

@ -674,7 +674,7 @@ struct BlifBackend : public Backend {
}
if (!top_module_name.empty())
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
log_error("Can't find top module `%s'!\n", top_module_name);
for (auto module : mod_list)
BlifDumper::dump(*f, module, design, config);

4
backends/btor/btor.cc
View file

@ -246,7 +246,7 @@ struct BtorWorker
string cell_list;
for (auto c : cell_recursion_guard)
cell_list += stringf("\n %s", log_id(c));
log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list);
}
cell_recursion_guard.insert(cell);
@ -1489,7 +1489,7 @@ struct BtorWorker
std::ofstream f;
f.open(info_filename.c_str(), std::ofstream::trunc);
if (f.fail())
log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", info_filename, strerror(errno));
for (auto &it : info_lines)
f << it;
f.close();

2
backends/edif/edif.cc
View file

@ -519,7 +519,7 @@ struct EdifBackend : public Backend {
continue;
} else {
for (auto &ref : it.second)
log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str());
log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first);
log_abort();
}
}

6
backends/firrtl/firrtl.cc
View file

@ -347,7 +347,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
auto modInstance = design->module(cell->type);
// Ensure that we actually have a module instance
if (modInstance == nullptr) {
log_error("Unknown cell type %s\n", cell->type.c_str());
log_error("Unknown cell type %s\n", cell->type);
return;
}
@ -505,14 +505,14 @@ struct FirrtlWorker
sinkExpr = firstName;
break;
default:
log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type, log_signal(it->second), dir);
break;
}
// Check for subfield assignment.
std::string bitsString = "bits(";
if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
if (sinkSig == nullptr)
log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
log_error("Unknown subfield %s.%s\n", cell_type, sinkExpr);
// Don't generate the assignment here.
// Add the source and sink to the "reverse_wire_map" and we'll output the assignment
// as part of the coalesced subfield assignments for this wire.

2
backends/functional/cxx.cc
View file

@ -268,7 +268,7 @@ struct FunctionalCxxBackend : public Backend
extra_args(f, filename, args, argidx, design);
for (auto module : design->selected_modules()) {
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
printCxx(*f, filename, module);
}
}

2
backends/functional/smtlib.cc
View file

@ -285,7 +285,7 @@ struct FunctionalSmtBackend : public Backend {
extra_args(f, filename, args, argidx, design);
for (auto module : design->selected_modules()) {
log("Processing module `%s`.\n", module->name.c_str());
log("Processing module `%s`.\n", module->name);
SmtModule smt(module);
smt.write(*f);
}

2
backends/functional/smtlib_rosette.cc
View file

@ -307,7 +307,7 @@ struct FunctionalSmtrBackend : public Backend {
}
for (auto module : design->selected_modules()) {
log("Processing module `%s`.\n", module->name.c_str());
log("Processing module `%s`.\n", module->name);
SmtrModule smtr(module);
smtr.write(*f);
}

2
backends/functional/test_generic.cc
View file

@ -143,7 +143,7 @@ struct FunctionalTestGeneric : public Pass
*/
for (auto module : design->selected_modules()) {
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
auto fir = Functional::IR::from_module(module);
for(auto node : fir)
std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";

4
backends/intersynth/intersynth.cc
View file

@ -100,13 +100,13 @@ struct IntersynthBackend : public Backend {
}
extra_args(f, filename, args, argidx);
log("Output filename: %s\n", filename.c_str());
log("Output filename: %s\n", filename);
for (auto filename : libfiles) {
std::ifstream f;
f.open(filename.c_str());
if (f.fail())
log_error("Can't open lib file `%s'.\n", filename.c_str());
log_error("Can't open lib file `%s'.\n", filename);
RTLIL::Design *lib = new RTLIL::Design;
Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
libs.push_back(lib);

4
backends/jny/jny.cc
View file

@ -553,7 +553,7 @@ struct JnyPass : public Pass {
ff->open(filename.c_str(), std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
invk << filename;
@ -568,7 +568,7 @@ struct JnyPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}

4
backends/json/json.cc
View file

@ -701,7 +701,7 @@ struct JsonPass : public Pass {
ff->open(filename.c_str(), std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
} else {
@ -714,7 +714,7 @@ struct JsonPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}
} JsonPass;

6
backends/rtlil/rtlil_backend.cc
View file

@ -458,7 +458,7 @@ struct RTLILBackend : public Backend {
design->sort();
log("Output filename: %s\n", filename.c_str());
log("Output filename: %s\n", filename);
*f << stringf("# Generated by %s\n", yosys_maybe_version());
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
@ -531,7 +531,7 @@ struct DumpPass : public Pass {
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
} else {
@ -543,7 +543,7 @@ struct DumpPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}
} DumpPass;

14
backends/simplec/simplec.cc
View file

@ -504,7 +504,7 @@ struct SimplecWorker
while (work->dirty)
{
if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty()))
log(" In %s:\n", work->log_prefix.c_str());
log(" In %s:\n", work->log_prefix);
while (!work->dirty_bits.empty() || !work->dirty_cells.empty())
{
@ -517,7 +517,7 @@ struct SimplecWorker
if (chunk.wire == nullptr)
continue;
if (verbose)
log(" Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
log(" Propagating %s.%s[%d:%d].\n", work->log_prefix, log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
funct_declarations.push_back(stringf(" // Updated signal in %s: %s", work->log_prefix, log_signal(chunk)));
}
@ -539,7 +539,7 @@ struct SimplecWorker
work->parent->set_dirty(parent_bit);
if (verbose)
log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset,
work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset);
}
@ -556,11 +556,11 @@ struct SimplecWorker
child->set_dirty(child_bit);
if (verbose)
log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset,
work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset);
} else {
if (verbose)
log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)),
log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix, log_id(std::get<0>(port)),
work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
work->set_dirty(std::get<0>(port));
}
@ -579,7 +579,7 @@ struct SimplecWorker
string hiername = work->log_prefix + "." + log_id(cell);
if (verbose)
log(" Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells));
log(" Evaluating %s (%s, best of %d).\n", hiername, log_id(cell->type), GetSize(work->dirty_cells));
if (activated_cells.count(hiername))
reactivated_cells.insert(hiername);
@ -630,7 +630,7 @@ struct SimplecWorker
void make_func(HierDirtyFlags *work, const string &func_name, const vector<string> &preamble)
{
log("Generating function %s():\n", func_name.c_str());
log("Generating function %s():\n", func_name);
activated_cells.clear();
reactivated_cells.clear();

8
backends/smt2/smt2.cc
View file

@ -130,7 +130,7 @@ struct Smt2Worker
for (auto &mem : memories)
{
if (is_smtlib2_module)
log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid.c_str());
log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid);
mem.narrow();
mem_dict[mem.memid] = &mem;
@ -620,11 +620,11 @@ struct Smt2Worker
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr));
if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str().c_str());
log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str());
}
else if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::minimize)){
decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str().c_str());
log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str());
}
bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
@ -1776,7 +1776,7 @@ struct Smt2Backend : public Backend {
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
template_f.open(args[++argidx]);
if (template_f.fail())
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
log_error("Can't open template file `%s'.\n", args[argidx]);
continue;
}
if (args[argidx] == "-bv" || args[argidx] == "-mem") {

4
backends/smv/smv.cc
View file

@ -756,7 +756,7 @@ struct SmvBackend : public Backend {
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
template_f.open(args[++argidx]);
if (template_f.fail())
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
log_error("Can't open template file `%s'.\n", args[argidx]);
continue;
}
if (args[argidx] == "-verbose") {
@ -795,7 +795,7 @@ struct SmvBackend : public Backend {
modules.erase(module);
if (module == nullptr)
log_error("Module '%s' not found.\n", stmt[1].c_str());
log_error("Module '%s' not found.\n", stmt[1]);
*f << stringf("-- SMV description generated by %s\n", yosys_maybe_version());

2
backends/spice/spice.cc
View file

@ -258,7 +258,7 @@ struct SpiceBackend : public Backend {
if (!top_module_name.empty()) {
if (top_module == NULL)
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
log_error("Can't find top module `%s'!\n", top_module_name);
print_spice_module(*f, top_module, design, neg, pos, buf, ncpf, big_endian, use_inames);
*f << stringf("\n");
}

6
backends/verilog/verilog_backend.cc
View file

@ -153,7 +153,7 @@ void reset_auto_counter(RTLIL::Module *module)
if (verbose)
for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it)
log(" renaming `%s' to `%s_%0*d_'.\n", it->first.c_str(), auto_prefix.c_str(), auto_name_digits, auto_name_offset + it->second);
log(" renaming `%s' to `%s_%0*d_'.\n", it->first, auto_prefix, auto_name_digits, auto_name_offset + it->second);
}
std::string next_auto_id()
@ -494,7 +494,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
std::ofstream extmem_f(extmem_filename, std::ofstream::trunc);
if (extmem_f.fail())
log_error("Can't open file `%s' for writing: %s\n", extmem_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", extmem_filename, strerror(errno));
else
{
Const data = mem.get_init_data();
@ -2632,7 +2632,7 @@ struct VerilogBackend : public Backend {
log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
continue;
}
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
module->sort();
dump_module(*f, "", module);
}