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Code Activity
14782 commits 99 branches 53 tags 47 MiB
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19 commits

Author SHA1 Message Date
Emil J. Tywoniak
4cbc92f50f quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
fcdd013c57 quicklogic: allow fractured mode on canonical dspv1 modules 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
f55da95ec8 quicklogic: update dspv2_sim.v to v1.1 Feb21 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
c451d8ebb9 synth_quicklogic: add -dspv2 to opt into v2 DSP blocks 2025-03-11 10:35:30 +01:00
Martin Povišer
e1074e0e4e qlf_k6n10f: Fix DSPV2 models 2025-03-11 10:35:01 +01:00
Martin Povišer
531374bec1 qlf_k6n10f: New ql_dsp pass, move to DSPV2 2025-03-11 10:35:01 +01:00
Zbigniew Jędrzejewski-Szmek
26a3478d8d Drop timestamp in generate_bram_types_sim.py 
I'm working on build reproducibility of Fedora packages, and this patch fixes
an issue observed in test rebuilds: the timestamp was set to the actual time
of the build, making builds nonreproducible.

Other "Generated by" strings do not include a timestamp, so drop it here too.
 2024-10-30 08:47:18 +01:00
Martin Povišer
e0fc48e196 quicklogic: Generate bram_types_sim.v at build time 2023-12-04 18:21:00 +01:00
Martin Povišer
22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Martin Povišer
e0a6a01ecb quicklogic: Add RAM_INIT to specialized BRAM models 2023-12-04 15:52:03 +01:00
Martin Povišer
4903f99f85 quicklogic: Add missing RAM_INIT param on TDP36K sim model 2023-12-04 15:52:03 +01:00
Martin Povišer
b602c0858f quicklogic: Set initial values on inferred TDP36K 2023-12-04 15:52:03 +01:00
Martin Povišer
532aca28ab quicklogic: Drop blackbox off adder_carry 2023-12-04 15:52:03 +01:00
Martin Povišer
4bb4fd358e ql_k6n10f: Remove support for parameter-configured DSP variety 2023-12-04 15:52:02 +01:00
N. Engelhardt
b80b1ab8b6 merge brams_final_map.v into brams_map.v 2023-12-04 15:52:02 +01:00
N. Engelhardt
20d864bbde add dsp inference 2023-12-04 15:52:02 +01:00
N. Engelhardt
6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-12-04 15:52:02 +01:00
N. Engelhardt
48c1fdc33d add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-12-04 15:52:02 +01:00