597 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	92b16718c9	twine: fix replayability, reduce TwineSearch usage	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	c3ffd67a5a	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	65f35a88eb	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	6a05403060	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	6d89534418	prevent IdString construction when looking up module from instance type	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	b01a3694f0	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	77ad54139e	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	7422b71802	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	1210d8e117	WIP	2026-07-20 12:27:02 +02:00
Emil J. Tywoniak	10436f31cd	WIP	2026-07-20 12:27:02 +02:00
Emil J. Tywoniak	a1d13b821e	rtlil: set Module::design before name at all construction sites	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	d7f88dd3a0	rtlil: evacuate src_id_ from AttrObject to per-Design meta vector	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	f017bb8a93	twine	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	fd67ce2b80	WIP	2026-07-17 23:48:54 +02:00
Emil J. Tywoniak	b3baa75528	signorm: disable passes that use rewrite_sigspecs	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	cd9b1191f2	signorm: disable in passes that use swap_names	2026-07-17 23:32:34 +02:00
Miodrag Milanovic	fd3ec58055	Remove leftover use of log_id	2026-06-24 08:04:48 +02:00
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
nella	6ffc938a75	Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup ... Add warnings and errors to `sim -r` with VCD code path	2026-06-22 09:02:32 +00:00
Catherine	a727e7f6e7	Migrate build system to CMake ... See #5895 for details. This commit does not include CI or documentation changes.	2026-06-03 08:58:10 +00:00
nella	886d0a7043	Merge branch 'main' into gus/sim-with-vcd-tuneup	2026-05-19 12:17:29 +02:00
nella	44a1abdade	Don't repeat VCD warnings + fixups.	2026-05-19 12:16:29 +02:00
Miodrag Milanovic	75dcbe03c6	Convert RTLIL::unescape_id of IdString to unescape()	2026-05-16 19:49:45 +02:00
Miodrag Milanovic	8bbc3c359c	Remove id2cstr uses in our code base	2026-05-16 19:49:45 +02:00
Miodrag Milanović	1d87cefd80	Merge pull request #5882 from YosysHQ/std_cpp20 ... Bump required standard to C++20	2026-05-15 13:13:43 +00:00
Miodrag Milanović	36eceed720	Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id ... Cleaning up log_id()	2026-05-15 11:07:43 +00:00
Miodrag Milanovic	90e019e319	Fix compiling on GCC11	2026-05-13 10:11:36 +02:00
Emil J. Tywoniak	3a150f2883	remove unused hashlib containers	2026-05-12 12:52:10 +02:00
Codexplorer	e41b969da2	Refactored uses of log_id()	2026-05-08 20:59:24 -07:00
Scott Ashcroft	23a05fcf35	Add comments to make sure it is clear scale is an exponent of 10	2026-04-23 17:22:14 +01:00
Scott Ashcroft	e69341cd5f	Make sure co-simulation only uses integer arithmetic	2026-04-23 17:22:14 +01:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
tondapusili	5b22e64d19	sim: cache sigmap in register_output_step_values	2026-03-24 16:10:11 -07:00
tondapusili	69219e6be0	sim: early-return from checkSignals in sim mode	2026-03-20 12:32:49 -07:00
Emil J. Tywoniak	498cb79abe	async2sync: explain dffsr control signal variable polarity	2026-03-09 20:18:56 +01:00
Emil J. Tywoniak	43ef4d2901	fixup! async2sync: $dffsr has undef output on S&R	2026-03-09 20:12:24 +01:00
Emil J. Tywoniak	ecb8b20f62	yosys: use newcelltypes for yosys_celltypes users	2026-03-04 12:39:44 +01:00
Emil J. Tywoniak	6f74c54c02	async2sync: $dffsr has undef output on S&R	2026-03-03 10:34:29 +01:00
Emil J. Tywoniak	a53104379d	clk2fflogic: $dffsr has undef output on S&R	2026-03-03 10:34:29 +01:00
Emil J	5f8489d36d	Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors ... equiv_induct: error on missing model	2026-02-25 15:39:31 +01:00
Gus Smith	366f98ae25	ADd clarification	2026-02-23 11:51:54 -08:00
Gus Smith	b454582f54	Detect undriven and error/warn	2026-02-20 11:00:59 -08:00
Gus Smith	cdc728b6f0	Suggest use of YW when possible	2026-02-20 09:33:51 -08:00
Emil J. Tywoniak	77f64de997	satgen: move report_missing_model here from equiv.h	2026-02-16 17:01:09 +01:00
Emil J. Tywoniak	81ea922512	sat: use the same cell import warnings as equiv	2026-02-16 16:54:26 +01:00
Gus Smith	1502e23371	Set solver from scratchpad or command line	2026-02-06 19:26:32 -08:00
Gus Smith	f062a0c8d6	Typo	2026-02-06 17:26:08 -08:00
Emil J. Tywoniak	8e73e2a306	sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency	2026-02-03 18:10:29 +01:00
Krystine Sherwin	5b317ee03c	sim.cc: Check eval err ... Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`. Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors. Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue. Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.	2025-12-15 12:08:07 +13:00